ocld.cpp

来自「SAMSUNG S3C6410 CPU BSP for winmobile6」· C++ 代码 · 共 1,751 行 · 第 1/5 页

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   /*                                                                   nTfTime */
   /*****************************************************************************/
    /* 1G DEMUX */
    {0xEC, 0x34, 0x00, 1024, 1, 20, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x35, 0x00, 1024, 1, 20, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 512M DEMUX */
    {0xEC, 0x24, 0x00,  512, 1, 10, 0, 2, 8, X16, ME_NO, RNG_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x25, 0x00,  512, 1, 10, 0, 2, 8, X16, ME_NO, RNG_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x24, 0x01,  512, 1, 10, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x25, 0x01,  512, 1, 10, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 1G DDP DEMUX */
    {0xEC, 0x3c, 0x00, 1024, 2, 20, 0, 2, 8, X16, ME_NO, RNG_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x3d, 0x00, 1024, 2, 20, 0, 2, 8, X16, ME_NO, RNG_LK, 50000, 350000, 2000000, 50},

    /* 2G DDP DEMUX */
    {0xEC, 0x4c, 0x00, 2048, 2, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x4d, 0x00, 2048, 2, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 2G DDP DEMUX based on 1Gb A-die */
    {0xEC, 0x4c, 0x01, 2048, 2, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x4d, 0x01, 2048, 2, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 256M DEMUX */
    {0xEC, 0x14, 0x00,  512, 1, 10, 0, 2, 8, X16, ME_OK, RNG_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x15, 0x00,  512, 1, 10, 0, 2, 8, X16, ME_OK, RNG_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x14, 0x01,  512, 1, 10, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x15, 0x01,  512, 1, 10, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 128M DEMUX */
    {0xEC, 0x04, 0x00,  256, 1,  5, 0, 2, 8, X16, ME_OK, RNG_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x05, 0x00,  256, 1,  5, 0, 2, 8, X16, ME_OK, RNG_LK, 50000, 350000, 2000000, 50},

    /* 1G MUX */
    {0xEC, 0x30, 0x00, 1024, 1, 20, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x31, 0x00, 1024, 1, 20, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 512M MUX */
    {0xEC, 0x20, 0x00,  512, 1, 10, 0, 2, 8, X16, ME_NO, RNG_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x21, 0x00,  512, 1, 10, 0, 2, 8, X16, ME_NO, RNG_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x20, 0x01,  512, 1, 10, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x21, 0x01,  512, 1, 10, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 1G DDP MUX */
    {0xEC, 0x38, 0x00, 1024, 2, 20, 0, 2, 8, X16, ME_NO, RNG_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x39, 0x00, 1024, 2, 20, 0, 2, 8, X16, ME_NO, RNG_LK, 50000, 350000, 2000000, 50},

    /* 2G DDP MUX */
    {0xEC, 0x48, 0x00, 2048, 2, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x49, 0x00, 2048, 2, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 2G DDP MUX based on 1Gb A-die */
    {0xEC, 0x48, 0x01, 2048, 2, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x49, 0x01, 2048, 2, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 256M MUX */
    {0xEC, 0x10, 0x00,  512, 1, 10, 0, 2, 8, X16, ME_OK, RNG_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x11, 0x00,  512, 1, 10, 0, 2, 8, X16, ME_OK, RNG_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x10, 0x01,  512, 1, 10, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x11, 0x01,  512, 1, 10, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 128M MUX */
    {0xEC, 0x00, 0x00,  256, 1,  5, 0, 2, 8, X16, ME_OK, RNG_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x01, 0x00,  256, 1,  5, 0, 2, 8, X16, ME_OK, RNG_LK, 50000, 350000, 2000000, 50},

    /* 2G DEMUX M-die */
    {0xEC, 0x44, 0x00, 2048, 1, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x45, 0x00, 2048, 1, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 4G DDP DEMUX  */
    {0xEC, 0x5c, 0x00, 4096, 2, 80, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x5d, 0x00, 4096, 2, 80, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 1G DEMUX A-die */
    {0xEC, 0x34, 0x01, 1024, 1, 20, 0, 2, 8, X16, ME_NO, BLK_LK, 50000, 350000, 2000000, 50}, // YJ
    {0xEC, 0x35, 0x01, 1024, 1, 20, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

     /* 512M DEMUX B-die */
    {0xEC, 0x24, 0x02,  512, 1, 10, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x25, 0x02,  512, 1, 10, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 2G MUX M-die */
    {0xEC, 0x40, 0x00, 2048, 1, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x41, 0x00, 2048, 1, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 4G DDP MUX */
    {0xEC, 0x58, 0x00, 4096, 2, 80, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x59, 0x00, 4096, 2, 80, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 1G MUX A-die */
    {0xEC, 0x30, 0x01, 1024, 1, 20, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x31, 0x01, 1024, 1, 20, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

     /* 512M MUX B-die */
    {0xEC, 0x20, 0x02,  512, 1, 10, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},
    {0xEC, 0x21, 0x02,  512, 1, 10, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 2G DDP DEMUX B-die */
    {0xEC, 0x4c, 0x02, 2048, 2, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 2G DDP MUX B-die */
    {0xEC, 0x48, 0x02, 2048, 2, 40, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 1G DEMUX B-die */
    {0xEC, 0x34, 0x02, 1024, 1, 20, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    /* 1G MUX B-die */
    {0xEC, 0x30, 0x02, 1024, 1, 20, 0, 2, 8, X16, ME_OK, BLK_LK, 50000, 350000, 2000000, 50},

    {0x00, 0x00, 0x00,   0,  0,  0, 0, 0, 0,   0,  0,   0, 0,   0,  0,     0}

};


/*****************************************************************************/
/* Local Function Declarations                                               */
/*****************************************************************************/
static VOID     _GetDevID   (UINT32  nDev, UINT16 *nMID,
                             UINT16 *nDID, UINT16 *nVID);
#if defined(STRICT_CHK)
static BOOL32   _StrictChk  (UINT32  nDev, UINT32  nPsn, UINT32 nScts);
#endif  /* #if defined(STRICT_CHK) */
static INT32 _M01_MRead(UINT32 nDev, UINT32 nPsn, UINT32 nScts, SGL *pstSGL, UINT8 *pSBuf, UINT32 nFlag);


/*****************************************************************************/
/* Local Macros                                                              */
/*****************************************************************************/
#define SET_PWR_FLAG(x)         {astONLDDev[x].bPower = TRUE32;}
#define CLEAR_PWR_FLAG(x)       {astONLDDev[x].bPower = FALSE32;}

/* Get Device Information */
#define GET_DEV_BADDR(n)        (astONLDDev[n].BaseAddr)
#define CHK_DEV_OPEN_FLAG(n)    (astONLDDev[n].bOpen)
#define CHK_DEV_PWR_FLAG(n)     (astONLDDev[n].bPower)
#define GET_DEV_MID(n)          (astONLDDev[n].pstDevSpec->nMID)
#define GET_DEV_DID(n)          (astONLDDev[n].pstDevSpec->nDID)
#define GET_DEV_VID(n)          (astONLDDev[n].pstDevSpec->nVID)
#define GET_NUM_OF_BLKS(n)      (astONLDDev[n].pstDevSpec->nNumOfBlks)
#define GET_PGS_PER_BLK(n)      (64)
#define GET_SCTS_PER_PG(n)       astONLDInfo[n].nSctsPerPG
#define GET_SCTS_PER_BLK(n)     (GET_SCTS_PER_PG(n) * GET_PGS_PER_BLK(n))
#define GET_NUM_OF_DIES(n)      (astONLDDev[n].pstDevSpec->nNumOfPlanes)
#define GET_ONENANDCON_BADDR(n)        ((n==ONENANDC0_MEM_VIRTADDR)?ONENANDC0_VIRTADDR:  \
                                           ((n==ONENANDC1_MEM_VIRTADDR)?ONENANDC1_VIRTADDR:NULL))
#define GET_ONENANDCON_NUM(n)        ((n==ONENANDC0_MEM_VIRTADDR)?0:1)

/* Get Operation Information */
#define GET_PREV_OP_TYPE(n)     (pstPrevOpInfo[n]->ePreOp)
#define GET_CUR_BUF_SEL(n)      (pstPrevOpInfo[n]->nBufSel)
#define GET_NXT_BUF_SEL(n)      ((pstPrevOpInfo[n]->nBufSel + 1) & 1)

#define GET_ONLD_MBUF_ADDR(x,nSct,nBuf)\
            (ONLD_DT_MB00_ADDR(x) + ((((nSct) & astONLDInfo[nDev].nSctSelSft) | ((nBuf) << astONLDInfo[nDev].nBufSelSft )) << 9))
#define GET_ONLD_SBUF_ADDR(x,nSct,nBuf)\
            (ONLD_DT_SB00_ADDR(x) + ((((nSct) & astONLDInfo[nDev].nSctSelSft) | ((nBuf) << astONLDInfo[nDev].nBufSelSft )) << 4))
#define GET_PBN(x, psn)         ((psn) >> astONLDInfo[x].nBlkSelSft)
#define GET_PPN(x, psn)         ((psn) >> astONLDInfo[x].nPgSelSft)


/*****************************************************************************/
/* Extern Function Declarations                                              */
/*****************************************************************************/

#if (OND_TRANS_MODE == OND_LDM)
extern "C"
{
void OneNand4burstPageRead(UINT32 nSrcAddr, UINT32 nDstAddr, UINT32 nDatSize);
void OneNand4burstPageWrite(UINT32 nSrcAddr, UINT32 nDstAddr, UINT32 nDatSize);
void OneNand8burstPageRead(UINT32 nSrcAddr, UINT32 nDstAddr, UINT32 nDatSize);
void OneNand8burstPageWrite(UINT32 nSrcAddr, UINT32 nDstAddr, UINT32 nDatSize);
}
#endif  // OND_TRANS_MODE

typedef enum OneNAND_CLOCK
{
	ONDNAND_RATIO_1_TO_HCLKx2 = 0,
	ONDNAND_RATIO_2_TO_HCLKx2 = 1,
	ONDNAND_RATIO_3_TO_HCLKx2 = 2,
	ONDNAND_RATIO_4_TO_HCLKx2 = 3,
}OneNAND_FlashClock;

typedef enum OneNAND_LATENCY
{
	eOND_LATENCY3 = 3, 
	eOND_LATENCY4 = 4, 
	eOND_LATENCY5 = 5,
	eOND_LATENCY6 = 6,
	eOND_LATENCY7 = 7,
	eOND_LATENCY8 = 0,
	eOND_LATENCY9 = 1,
	eOND_LATENCY10 = 2
}OneNAND_eLATENCY;

typedef enum OneNAND_MODE
{
	eOND_ASYNC, eOND_SYNC_CONT, eOND_SYNC_BURST4, eOND_SYNC_BURST8, eOND_SYNC_BURST16, eOND_SYNC_BURST32, eOND_RM_SYNC_WM_ASYNC_BURST16
}OneNAND_eMODE;


/*****************************************************************************/
/* OneNAND Register Address Definitions                                      */
/*****************************************************************************/

// MAP command
#define BUFFER			(0<<24)
#define ARRAY_RW		(1<<24)
#define COMMANDS		(2<<24)
#define DIRECT_ACCESS	(3<<24)

#define ONLD_BUFFER_BASE(n)    (n + BUFFER)
#define ONLD_ARRAY_BASE(n)     (n + ARRAY_RW)
#define ONLD_CMD_BASE(n)       (n + COMMANDS)
#define ONLD_DIRECT_BASE(n)    (n + DIRECT_ACCESS)

#define CMAKE_FBA(n,addr)    ((addr & astONLDMemAddr[n].nFBAMask) << astONLDMemAddr[n].nFBAShift)
#define CMAKE_FPA(n,addr)    ((addr & astONLDMemAddr[n].nFPAMask) << astONLDMemAddr[n].nFPAShift)
#define CMAKE_FSA(n,addr)    ((addr & astONLDMemAddr[n].nFSAMask) << astONLDMemAddr[n].nFSAShift)
#define CMAKE_DFS(n,addr)    ((addr & astONLDMemAddr[n].nDFSDBSMask) << astONLDMemAddr[n].nDFSDBSShift)

#define ONLD_BUFFER_DEF(n,a)               (ONLD_BUFFER_BASE(n) + ((0xffff & a)<<1))
#define ONLD_ARRAY_DEF(n,a,b,p)               (ONLD_ARRAY_BASE(a) + CMAKE_FBA(n,b) + CMAKE_FPA(n,p))
#define ONLD_CMD_DEF(n,a,b,p)               (ONLD_CMD_BASE(a) + CMAKE_FBA(n,b) + CMAKE_FPA(n,p))
#define ONLD_DIRECT_DEF(n,a)               (ONLD_DIRECT_BASE(n) + ((0xffff & a)<<2))

#define ONLD_READ_BUFFER(n,addr)              (*(volatile UINT32*)ONLD_BUFFER_DEF(n,addr))
#define ONLD_WRITE_BUFFER(n,addr,data)        ((*(volatile UINT32*)ONLD_BUFFER_DEF(n,addr)) = data)
#define ONLD_READ_ARRAY(n,a,b,p)          (*(volatile UINT32*)ONLD_ARRAY_DEF(n,a,b,p))
#define ONLD_WRITE_ARRAY(n,a,b,p,data)    ((*(volatile UINT32*)ONLD_ARRAY_DEF(n,a,b,p)) = data)
#define ONLD_READ_CMD(n,a,b,p)            (*(volatile UINT32*)ONLD_CMD_DEF(n,a,b,p))
#define ONLD_WRITE_CMD(n,a,b,p,data)     ((*(volatile UINT32*)ONLD_CMD_DEF(n,a,b,p)) = data)
#define ONLD_READ_DIRECT(n,addr)              (*(volatile UINT32*)ONLD_DIRECT_DEF(n,addr))
#define ONLD_WRITE_DIRECT(n,addr,data)        ((*(volatile UINT32*)ONLD_DIRECT_DEF(n,addr)) = data)




// OneNAND Controller Page Length
#define ONDC_MAIN		(2048)
#define ONDC_MAINSPARE	(2048+64)


//////////
// Function Name : ONENAND_SetMemSpace
// Function Description : Set the OneNand Device Infomation to Controller Register & Set variable about the MEM_ADDR field Information
// Input : 	Controller - OneNand Controller Port Number 
// Version : v0.1
void ONENAND_SetMemSpace(UINT32 nDev, UINT16 *nDID)
{
	UINT32 uDeviceDensity, uDeviceDDP;
	UINT32 nBAddr;
	UINT32 nCAddr;

    ONLD_DBG_PRINT((TEXT("[ONLD :  IN] ++ONENAND_SetMemSpace() nDev = %d\r\n"), nDev));

	nBAddr = GET_DEV_BADDR(nDev);
	nCAddr = GET_ONENANDCON_BADDR(nBAddr);

	uDeviceDensity = (*nDID & 0xF0)>>4;
	uDeviceDDP     = (*nDID & 0x8)>>3;

	switch(uDeviceDensity)
	{
		case 0 :
				OCLD_REG_FBA_WIDTH(nCAddr) = 8;
				OCLD_REG_FPA_WIDTH(nCAddr) = 6;
				OCLD_REG_FSA_WIDTH(nCAddr) = 1;
				OCLD_REG_DBS_DFS_WIDTH(nCAddr) = 0;
				astONLDMemAddr[nDev].nFBAShift = 12;
				astONLDMemAddr[nDev].nFPAShift = 6;
				astONLDMemAddr[nDev].nFSAShift = 4;
				astONLDMemAddr[nDev].nFBAMask  = 0xFF;
				astONLDMemAddr[nDev].nFPAMask  = 0x3F;
				astONLDMemAddr[nDev].nFSAMask  = 0x1;
				break;
		case 1 :
				OCLD_REG_FBA_WIDTH(nCAddr) = 9;
				OCLD_REG_FPA_WIDTH(nCAddr) = 6;
				OCLD_REG_FSA_WIDTH(nCAddr) = 1;
				OCLD_REG_DBS_DFS_WIDTH(nCAddr) = 0;
				astONLDMemAddr[nDev].nFBAShift = 12;
				astONLDMemAddr[nDev].nFPAShift = 6;
				astONLDMemAddr[nDev].nFSAShift = 4;
				astONLDMemAddr[nDev].nFBAMask  = 0x1FF;
				astONLDMemAddr[nDev].nFPAMask  = 0x3F;
				astONLDMemAddr[nDev].nFSAMask  = 0x1;
				break;
		case 2 :
				OCLD_REG_FBA_WIDTH(nCAddr) = 9;
				OCLD_REG_FPA_WIDTH(nCAddr) = 6;
				OCLD_REG_FSA_WIDTH(nCAddr) = 2;
				OCLD_REG_DBS_DFS_WIDTH(nCAddr) = 0;
				astONLDMemAddr[nDev].nFBAShift = 12;
				astONLDMemAddr[nDev].nFPAShift = 6;
				astONLDMemAddr[nDev].nFSAShift = 4;
				astONLDMemAddr[nDev].nFBAMask  = 0x1FF;
				astONLDMemAddr[nDev].nFPAMask  = 0x3F;
				astONLDMemAddr[nDev].nFSAMask  = 0x3;
				break;
		case 3 :
				OCLD_REG_FPA_WIDTH(nCAddr) = 6;
				OCLD_REG_FSA_WIDTH(nCAddr) = 2;
				if(uDeviceDDP)
				{
					OCLD_REG_FBA_WIDTH(nCAddr) = 9;
					OCLD_REG_DBS_DFS_WIDTH(nCAddr) = 1;
					astONLDMemAddr[nDev].nDFSDBSMask = 1;
				}
				else
				{
					OCLD_REG_FBA_WIDTH(nCAddr) = 10;
					OCLD_REG_DBS_DFS_WIDTH(nCAddr) = 0;
					astONLDMemAddr[nDev].nDFSDBSMask = 0;
				}
				astONLDMemAddr[nDev].nFBAShift = 12;
				astONLDMemAddr[nDev].nFPAShift = 6;
				astONLDMemAddr[nDev].nFSAShift = 4;
				astONLDMemAddr[nDev].nFBAMask  = 0x3FF;
				astONLDMemAddr[nDev].nFPAMask  = 0x3F;
				astONLDMemAddr[nDev].nFSAMask  = 0x3;
				break;
		case 4 :
				OCLD_REG_FPA_WIDTH(nCAddr) = 6;
				OCLD_REG_FSA_WIDTH(nCAddr) = 2;
				if(uDeviceDDP)
				{
					OCLD_REG_FBA_WIDTH(nCAddr) = 10;
					OCLD_REG_DBS_DFS_WIDTH(nCAddr) = 1;
					astONLDMemAddr[nDev].nDFSDBSMask = 1;
				}
				else
				{
					OCLD_REG_FBA_WIDTH(nCAddr) = 11;
					OCLD_REG_DBS_DFS_WIDTH(nCAddr) = 0;
					astONLDMemAddr[nDev].nDFSDBSMask = 0;
				}
				astONLDMemAddr[nDev].nFBAShift = 12;
				astONLDMemAddr[nDev].nFPAShift = 6;
				astONLDMemAddr[nDev].nFSAShift = 4;
				astONLDMemAddr[nDev].nFBAMask  = 0x7FF;
				astONLDMemAddr[nDev].nFPAMask  = 0x3F;
				astONLDMemAddr[nDev].nFSAMask  = 0x3;
				break;	
		case 5 :
				OCLD_REG_FPA_WIDTH(nCAddr) = 6;
				OCLD_REG_FSA_WIDTH(nCAddr) = 2;
				if(uDeviceDDP)
				{
					OCLD_REG_FBA_WIDTH(nCAddr) = 11;
					OCLD_REG_DBS_DFS_WIDTH(nCAddr) = 1;

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