startup.s
来自「SAMSUNG S3C6410 CPU BSP for winmobile6」· S 代码 · 共 825 行 · 第 1/2 页
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;------------------------------------------------------------------------------
;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;------------------------------------------------------------------------------
;
; File: startup.s
;
; Kernel startup routine for Samsung SMDK6410 board. Hardware is
; initialized in boot loader - so there isn't much code at all.
;
;------------------------------------------------------------------------------
INCLUDE kxarm.h
INCLUDE s3c6410.inc
INCLUDE image_cfg.inc
IMPORT OALClearUTLB
IMPORT OALClearITLB
IMPORT OALClearDTLB
IMPORT OALFlushICache
IMPORT OALFlushDCache
IMPORT System_EnableICache
IMPORT System_SetSyncMode
IMPORT System_SetAsyncMode
IMPORT System_DisableVIC
IMPORT System_EnableBP
IMPORT System_WaitForInterrupt
IMPORT KernelStart
TEXTAREA
INCLUDE oemaddrtab_cfg.inc
;------------------------------------------------------------------------------
;
; Macro for Sleep Code
;
;------------------------------------------------------------------------------
SYSCTL_SBZ_MASK EQU (0xCC1A0000)
SYSCTL_SBO_MASK EQU (0x00000070)
;MMUTTB_SBZ_MASK EQU (0x00003FE0) ; for 16KB Boundary Size of TTB0
MMUTTB_SBZ_MASK EQU (0x00001FE0) ; for 8KB Boundary Size of TTB0
;MMUTTB_SBZ_MASK EQU (0x00000FE0) ; for 4KB Boundary Size of TTB0
;MMUTTB_SBZ_MASK EQU (0x000007E0) ; for 2KB Boundary Size of TTB0
;------------------------------------------------------------------------------
;
; Macro for LED on SMDK Board (GPN[15:12])
;
; LED_ON for physical address domain
; VLED_ON for virtual address domain
;
;------------------------------------------------------------------------------
MACRO
LED_ON $data
ldr r10, =GPNPUD
ldr r11, [r10]
bic r11, r11, #0xFF000000 ; Pull-Up-Down Disable
str r11, [r10]
ldr r10, =GPNDAT
ldr r11, [r10]
bic r11, r11, #0xF000
ldr r12, =$data
mov r12, r12, lsl #12 ; [15:12]
orr r11, r11, r12
str r11, [r10]
ldr r10, =GPNCON
ldr r11, [r10]
bic r11, r11, #0xFF000000
orr r11, r11, #0x55000000 ; GPN[15:12] Output .
str r11, [r10]
MEND
MACRO
VLED_ON $data
ldr r10, =vGPNPUD
ldr r11, [r10]
bic r11, r11, #0xFF000000 ; Pull-Up-Down Disable
str r11, [r10]
ldr r10, =vGPNDAT
ldr r11, [r10]
bic r11, r11, #0xF000
ldr r12, =$data
mov r12, r12, lsl #12 ; [15:12]
orr r11, r11, r12
str r11, [r10]
ldr r10, =vGPNCON
ldr r11, [r10]
bic r11, r11, #0xFF000000
orr r11, r11, #0x55000000 ; GPN[15:12] Output .
str r11, [r10]
MEND
;------------------------------------------------------------------------------
; End of Macro
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;
; StartUp Entry
;
; Main entry point for CPU initialization.
;
;------------------------------------------------------------------------------
LEAF_ENTRY StartUp
b ResetHandler ; Jump over Power-Off code
HandlerUndef
b HandlerUndef
HandlerSWI
b HandlerSWI
HandlerPabort
b HandlerPabort
HandlerDabort
b HandlerDabort
HandlerReserved
b HandlerReserved
HandlerIRQ
b HandlerIRQ
HandlerFIQ
b HandlerFIQ
;------------------------------------------------------------------------------
; End of StartUp
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;
; ResetHandler Function
;
; Reset Exception Handler
;
;------------------------------------------------------------------------------
ResetHandler
;------------------------------------
; Enable Instruction Cache
;------------------------------------
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 ; Invalidate Entire I&D Cache
bl System_EnableICache ; Enable I Cache
;------------------------------------
; Peripheral Port Setup
;------------------------------------
ldr r0, =0x70000013 ; Base Addres : 0x70000000, Size : 256 MB (0x13)
mcr p15,0,r0,c15,c2,4
;------------------------------------
; Interrupt Disable
;------------------------------------
ldr r0, =VIC0INTENCLEAR
ldr r1, =0xFFFFFFFF;
str r1, [r0]
ldr r0, =VIC1INTENCLEAR
ldr r1, =0xFFFFFFFF;
str r1, [r0]
;---------------------------------------------------
; Enable VFP via Coprocessor Access Cotrol Register
;---------------------------------------------------
mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #0x00F00000
mcr p15, 0, r0, c1, c0, 2
;------------------------------------
; Disable WatchDog Timer
;------------------------------------
ldr r0, =WTCON
ldr r1, =0x0
str r1, [r0]
[ CHANGE_PLL_CLKDIV_ON_KERNEL
;-----------------------------------------------
; Change Operation Mode to Sync Mode or Async Mode
;-----------------------------------------------
ldr r0, =OTHERS
ldr r1, [r0]
and r1, r1, #0x40
cmp r1, #0x40 ; OTHERS[6] = 0:AsyncModde 1:SyncMode
[ CPU_NAME = S3C6410
[ (SYNCMODE)
bne System_SetSyncMode
|
beq System_SetAsyncMode
]
]
[ CPU_NAME = S3C6400
beq System_SetAsyncMode
]
;---------------------------------------
; Check PLL and CLKDIV
;---------------------------------------
ldr r3, =0x83FF3F07 ; Mask for APLL_CON/MPLL_CON
ldr r4, =0x80FF3F07 ; Mask for EPLL_CON0
ldr r5, =0x0000FFFF ; Mask for EPLL_CON1
ldr r6, =0x0003FF17 ; Mask for CLKDIV0
ldr r0, =APLL_CON ; Check APLL
ldr r1, [r0]
and r1, r1, r3
ldr r2, =((1<<31)+(APLL_MVAL<<16)+(APLL_PVAL<<8)+(APLL_SVAL)) ; APLL_CON value to configure
cmp r1, r2
bne PLL_NeedToConfigure
ldr r0, =MPLL_CON ; Check MPLL
ldr r1, [r0]
and r1, r1, r3
ldr r2, =((1<<31)+(MPLL_MVAL<<16)+(MPLL_PVAL<<8)+(MPLL_SVAL)) ; MPLL_CON value to configure
cmp r1, r2
bne PLL_NeedToConfigure
ldr r0, =EPLL_CON0 ; Check EPLL_CON0
ldr r1, [r0]
and r1, r1, r4
ldr r2, =((1<<31)+(EPLL_MVAL<<16)+(EPLL_PVAL<<8)+(EPLL_SVAL)) ; EPLL_CON0 value to configure
cmp r1, r2
bne PLL_NeedToConfigure
ldr r0, =EPLL_CON1 ; Check EPLL_CON1
ldr r1, [r0]
and r1, r1, r5
ldr r2, =EPLL_KVAL ; EPLL_CON1 value to configure
cmp r1, r2
bne PLL_NeedToConfigure
ldr r0, =CLK_DIV0 ; Check CLKDIV0
ldr r1, [r0]
and r1, r1, r6
[ CPU_NAME = S3C6410
ldr r2, =((PCLK_DIV<<12)+(HCLKx2_DIV<<9)+(HCLK_DIV<<8)+(MPLL_DIV<<4)+(APLL_DIV<<0)) ; CLKDIV0 value to configure
]
[ CPU_NAME = S3C6400
ldr r2, =((OND_DIV<<16)+(PCLK_DIV<<12)+(HCLKx2_DIV<<9)+(HCLK_DIV<<8)+(MPLL_DIV<<4)+(APLL_DIV<<0)) ; CLKDIV0 value to configure
]
cmp r1, r2
bne CLKDIV_NeedToConfigure
b PLL_CLKDIV_AlreadyConfigured ; APLL/MPLL/EPLL and CLKDIV0 is already configured
;------------------------------------
; Prepare to Change PLL
;------------------------------------
PLL_NeedToConfigure
[ CPU_NAME = S3C6410
;------------------------------------
; Disable PLL Clock Out
;------------------------------------
ldr r0, =CLK_SRC
ldr r1, [r0]
bic r1, r1, #0x7 ; FIN out
str r1, [r0]
ldr r0, =CLK_DIV0
ldr r1, [r0]
bic r1, r1, #0xff00
bic r1, r1, #0xff
[ SYNCMODE
ldr r2, =0x1300 ; ARM:HCLKx2:HCLK:PCLK = 1:2:2:2
|
ldr r2, =0x1100 ; ARM:HCLKx2:HCLK:PCLK = 1:1:2:2
]
orr r1, r1, r2
str r1, [r0]
]
[ CPU_NAME = S3C6400
ldr r0, =CLK_DIV0
ldr r1, [r0]
bic r1, r1, #0xff00
bic r1, r1, #0xff
ldr r2, =0x1100 ; ARM:HCLKx2:HCLK:PCLK = 1:1:2:2
orr r1, r1, r2
str r1, [r0]
]
;------------------------------------
; Change PLL Value
;------------------------------------
ldr r1, =0x4B1 ; Lock Time : 0x4b1 (100us @Fin12MHz) for APLL/MPLL
ldr r2, =0xE13 ; Lock Time : 0xe13 (300us @Fin12MHz) for EPLL
ldr r0, =APLL_LOCK
str r1, [r0] ; APLL Lock Time
str r1, [r0, #0x4] ; MPLL Lock Time
str r2, [r0, #0x8] ; EPLL Lock Time
ldr r0, =APLL_CON
ldr r1, =((1<<31)+(APLL_MVAL<<16)+(APLL_PVAL<<8)+(APLL_SVAL))
str r1, [r0]
ldr r0, =MPLL_CON
ldr r1, =((1<<31)+(MPLL_MVAL<<16)+(MPLL_PVAL<<8)+(MPLL_SVAL))
str r1, [r0]
ldr r0, =EPLL_CON1
ldr r1, =EPLL_KVAL
str r1, [r0]
ldr r0, =EPLL_CON0
ldr r1, =((1<<31)+(EPLL_MVAL<<16)+(EPLL_PVAL<<8)+(EPLL_SVAL))
str r1, [r0]
;------------------------------------
; Set System Clock Divider
;------------------------------------
CLKDIV_NeedToConfigure
ldr r0, =CLK_DIV0
ldr r1, [r0]
bic r1, r1, #0x30000
bic r1, r1, #0xff00
bic r1, r1, #0xff
[ CPU_NAME = S3C6410
ldr r2, =((PCLK_DIV<<12)+(HCLKx2_DIV<<9)+(HCLK_DIV<<8)+(MPLL_DIV<<4)+(APLL_DIV<<0)) ; CLKDIV0 value to configure
]
[ CPU_NAME = S3C6400
ldr r2, =((OND_DIV<<16)+(PCLK_DIV<<12)+(HCLKx2_DIV<<9)+(HCLK_DIV<<8)+(MPLL_DIV<<4)+(APLL_DIV<<0)) ; CLKDIV0 value to configure
]
orr r1, r1, r2
str r1, [r0]
;------------------------------------
; Enable PLL Clock Out
;------------------------------------
ldr r0, =CLK_SRC
ldr r1, [r0]
orr r1, r1, #0x7 ; PLL Clockout
str r1, [r0] ; System will be waiting for PLL unlocked after this instruction
PLL_CLKDIV_AlreadyConfigured
] ; CHANGE_PLL_CLKDIV_ON_KERNEL
;------------------------------------
; Expand Memory Port 1 to x32
;------------------------------------
ldr r0, =MEM_SYS_CFG
ldr r1, [r0]
bic r1, r1, #0x80 ; ADDR_EXPAND to "0"
str r1, [r0]
;------------------------------------
; Store BSP Data
;------------------------------------
ldr r0, =INFORM0
ldr r1, =0x64107618 ; June 18, 2007
str r1, [r0]
;------------------------------------
; Power Management Routine
; (WakeUp Processing)
;------------------------------------
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