init.c

来自「SAMSUNG S3C6410 CPU BSP for winmobile6」· C语言 代码 · 共 481 行 · 第 1/2 页

    // 3) configure pull-up resistor(GPnPUD)


	// setup GPNDAT[9] as Input port to check Hive-Clean option
	s6410IOP->GPNDAT |= (1<<9);
	s6410IOP->GPNCON = (s6410IOP->GPNCON & ~(0x3<<18)) | (0<<18);
	s6410IOP->GPNPUD = (s6410IOP->GPNPUD & ~(0x3<<18)) | (0<<18);

}
*/

static void InitializeGPIO()
{
	volatile S3C6410_GPIO_REG *pGPIOReg = (S3C6410_GPIO_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_GPIO, FALSE);

	OALMSG(TRUE, (L"[OAL] ++InitializeGPIO()\r\n"));

	// setup GPNDAT[9] as Input port to check Hive-Clean option
	pGPIOReg->GPNDAT |= (1<<9);
	pGPIOReg->GPNCON = (pGPIOReg->GPNCON & ~(0x3<<18)) | (0<<18);
	pGPIOReg->GPNPUD = (pGPIOReg->GPNPUD & ~(0x3<<18)) | (0<<18);

	// TODO: What port need initialization???

	OALMSG(TRUE, (L"[OAL] --InitializeGPIO()\r\n"));
}

static void InitializeINFORMSFR(void)
{
	volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);

	OALMSG(TRUE, (L"[OAL] ++InitializeINFORMSFR()\r\n"));

	pSysConReg->INFORM0 = 0x64100000;
	
	OALMSG(TRUE, (L"[OAL] --InitializeINFORMSFR()\r\n"));
}

static void InitializeCLKGating(void)
{
	volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);

	OALMSG(TRUE, (L"[OAL] InitializeCLKGating()\r\n"));

	// CAUTION !!!
	// HCLK_IROM, HCLK_MEM1, HCLK_MEM0, HCLK_MFC Should be Always On for power Mode
	// Because we can not expect when Warm Reset will be triggered..

	pSysConReg->HCLK_GATE = (0x3<<30)	// Reserved
							|(0<<29)	// USB Host
							|(0<<28)	// Security Sub-system
							|(0<<27)	// SDMA1
							|(0<<26)	// SDMA0, USB Host (EVT0)
							|(1<<25)	// Internal ROM				<--- Always On (for Power Mode)
							|(1<<24)	// DDR1					<--- Always On
							|(0<<23)	// DDR0
							|(1<<22)	// DMC1					<--- Always On (for Power Mode)
							|(1<<21)	// DMC0, SROM, OneNAND, NFCON, CFCON	<--- Always On (for Power Mode)
							|(0<<20)	// USB OTG
							|(0<<19)	// HSMMC2
							|(0<<18)	// HSMMC1
							|(0<<17)	// HSMMC0
							|(0<<16)	// MDP Interface
#ifdef ULDR
							|(1<<15)	// Direct Host Interface (MSM I/F)
#else
							|(0<<15)	// Direct Host Interface (MSM I/F)
#endif
							|(0<<14)	// Indirect Host Interface
							|(0<<13)	// DMA1
							|(0<<12)	// DMA0
							|(0<<11)	// Jpeg
							|(0<<10)	// Cam Interface
							|(0<<9)		// TV Scaler
							|(0<<8)		// 2D
							|(0<<7)		// TV Encoder
							|(1<<6)		// Reserved
							|(0<<5)		// Post Processor
							|(0<<4)		// Rotator
							|(1<<3)		// Display Controller			<--- Always On
							|(0<<2)		// Trust Interrupt Controller
							|(1<<1)		// Interrupt Controller		<--- Always On
							|(1<<0);		// MFC					<--- Always On (for Power Mode)

	pSysConReg->PCLK_GATE = (0x7F<<25)	// Reserved
							|(0<<24)	// Security Key
							|(0<<23)	// CHIP ID
							|(0<<22)	// SPI1
							|(0<<21)	// SPI0
							|(0<<20)	// HSI Receiver
							|(0<<19)	// HSI Transmitter
							|(1<<18)	// GPIO					<--- Always On
							|(0<<17)	// IIC
							|(0<<16)	// IIS1
							|(0<<15)	// IIS0
							|(0<<14)	// AC97 Interface
							|(0<<13)	// TZPC
							|(1<<12)	// Touch Screen & ADC		<--- Always On
							|(0<<11)	// Keypad
							|(0<<10)	// IrDA
							|(0<<9)		// PCM1
							|(0<<8)		// PCM0
							|(1<<7)		// PWM Timer				<--- Always On
							|(1<<6)		// RTC					<--- Always On
							|(0<<5)		// WatchDog Timer
#if 		(DEBUG_PORT == DEBUG_UART0)				// Be Careful to Serial KITL Clock
							|(0<<4)		// UART3
							|(0<<3)		// UART2
							|(0<<2)		// UART1
							|(1<<1)		// UART0					<--- Always On
#elif	(DEBUG_PORT == DEBUG_UART1)				// Be Careful to Serial KITL Clock
							|(0<<4)		// UART3
							|(0<<3)		// UART2
							|(1<<2)		// UART1					<--- Always On
							|(0<<1)		// UART0
#elif	(DEBUG_PORT == DEBUG_UART2)				// Be Careful to Serial KITL Clock
							|(0<<4)		// UART3
							|(1<<3)		// UART2					<--- Always On
							|(0<<2)		// UART1
							|(0<<1)		// UART0
#elif	(DEBUG_PORT == DEBUG_UART3)				// Be Careful to Serial KITL Clock
							|(1<<4)		// UART3					<--- Always On
							|(0<<3)		// UART2
							|(0<<2)		// UART1
							|(0<<1)		// UART0
#endif
							|(0<<0);		// MFC

	pSysConReg->SCLK_GATE = (0x1<<31)	// Reserved
							|(0<<30)	// USB Host
							|(0<<29)	// MMC2 48
							|(0<<28)	// MMC1 48
							|(0<<27)	// MMC0 48
							|(0<<26)	// MMC2
							|(0<<25)	// MMC1
							|(0<<24)	// MMC0
							|(0<<23)	// SPI1 48
							|(0<<22)	// SPI0 48
							|(0<<21)	// SPI1
							|(0<<20)	// SPI0
							|(0<<19)	// DAC 27
							|(0<<18)	// TV Encoder 27
							|(0<<17)	// TV Scaler 27
							|(0<<16)	// TV Scaler
							|(0<<15)	// Display Controller 27
							|(1<<14)	// Display Controller			<--- Always On
							|(0<<13)	// Post Processor1 27
							|(0<<12)	// Post Processor0 27
							|(0<<11)	// Post Processor1
							|(0<<10)	// Post Processor0
							|(0<<9)		// Audio1
							|(0<<8)		// Audio0
							|(0<<7)		// Security Block
							|(0<<6)		// IrDA
							|(1<<5)		// UART0~3				<--- Always On
							|(0<<4)		// OneNAND
							|(0<<3)		// MFC		
							|(0<<2)		// Camera Interface
							|(0<<1)		// Jpeg
							|(1<<0);		// Reserved
}


static void InitializeBlockPower(void)
{
	volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);

	OALMSG(TRUE, (L"[OAL] InitializeBlockPower()\r\n"));

	pSysConReg->NORMAL_CFG = (1<<31)		// Reserved
							|(0<<30)		// IROM Block Off	(Internal 32KB Boot ROM)
							|(0x1FFF<<17)	// Reserved
							|(1<<16)		// DOMAIN_ETM On	(JTAG not connected when ETM off)
							|(1<<15)		// DOMAIN_S Off	(SDMA0, SDMA1, Security System)
							|(1<<14)		// DOMAIN_F On	(LCD, Post, Rotator)
							|(0<<13)		// DOMAIN_P Off	(TV Scaler, TV Encoder, 2D)
							|(0<<12)		// DOMAIN_I Off	(Cam I/F, Jpeg)
							|(0x3<<10)		// Reserved
							|(0<<9)			// DOMAIN_V Off	(MFC)
							|(0x100);		// Reserved
}

static void InitializeCLKSource(void)
{
	volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);

	OALMSG(TRUE, (L"[OAL] InitializeCLKSource()\r\n"));

	pSysConReg->CLK_SRC = (pSysConReg->CLK_SRC & ~(0xFFFFFFF0))
							|(0<<31)	// TV27_SEL	-> 27MHz
							|(0<<30)	// DAC27		-> 27MHz
							|(0<<28)	// SCALER_SEL	-> MOUT_EPLL
							|(1<<26)	// LCD_SEL	-> Dout_MPLL
							|(0<<24)	// IRDA_SEL	-> MOUT_EPLL
							|(0<<22)	// MMC2_SEL	-> MOUT_EPLL
							|(0<<20)	// MMC1_SEL	-> MOUT_EPLL
							|(0<<18)	// MMC0_SEL	-> MOUT_EPLL
							|(0<<16)	// SPI1_SEL	-> MOUT_EPLL
							|(0<<14)	// SPI0_SEL	-> MOUT_EPLL
							|(0<<13)	// UART_SEL	-> MOUT_EPLL
							|(0<<10)	// AUDIO1_SEL	-> MOUT_EPLL
							|(0<<7)		// AUDIO0_SEL	-> MOUT_EPLL
							|(0<<5)		// UHOST_SEL	-> 48MHz
							|(0<<4);		// MFCCLK_SEL	-> HCLKx2 (0:HCLKx2, 1:MoutEPLL)

	// TODO: What Clock need dividing???
	
	pSysConReg->CLK_DIV0 = (pSysConReg->CLK_DIV0 & ~(0xf<<28))
							| ((2-1)<<28);	// MFCCLK = SRC/2

	//pSysConReg->CLK_DIV1;
	//pSysConReg->CLK_DIV2;
}

#if	(CPU_NAME == S3C6410)
//--------------------------------------------------------------------
//48MHz clock source for usb host1.1, IrDA, hsmmc, spi is shared with otg phy clock.
//So, initialization and reset of otg phy shoud be done on initial booting time.
//--------------------------------------------------------------------
static void InitializeOTGCLK(void)
{
	volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
	volatile OTG_PHY_REG *pOtgPhyReg = (OTG_PHY_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_USBOTG_PHY, FALSE);

	pSysConReg->HCLK_GATE |= (1<<20);

	pSysConReg->OTHERS |= (1<<16);

	pOtgPhyReg->OPHYPWR = 0x0;  // OTG block, & Analog bock in PHY2.0 power up, normal operation
	pOtgPhyReg->OPHYCLK = 0x20; // Externel clock/oscillator, 48MHz reference clock for PLL
	pOtgPhyReg->ORSTCON = 0x1;
	Delay(100);	
	pOtgPhyReg->ORSTCON = 0x0;
	Delay(100);	//10000

	pSysConReg->HCLK_GATE &= ~(1<<20);

}
#endif