📄 off.c
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*pBuffer++ = pDMACReg->DMACC7LLI;
*pBuffer++ = pDMACReg->DMACC7Control0;
*pBuffer++ = pDMACReg->DMACC7Control1;
*pBuffer++ = pDMACReg->DMACC7Configuration;
}
static void S3C6410_RestoreState_DMACon(void *pDMAC, UINT32 *pBuffer)
{
volatile S3C6410_DMAC_REG *pDMACReg;
pDMACReg = (S3C6410_DMAC_REG *)pDMAC;
//DMACIntStatus; // Read-Only
//DMACIntTCStatus; // Read-Only
//DMACIntTCClear; // Clear Register
//DMACIntErrStatus; // Read-Only
//DMACIntErrClear; // Clear Register
//DMACRawIntTCStatus; // Read-Only
//DMACRawIntErrStatus; // Read-Only
//DMACEnbldChns; // Read-Only
//DMACSoftBReq; // No use
//DMACSoftSReq; // No use
//DMACSoftLBReq; // No use
//DMACSoftLSReq; // No use
pDMACReg->DMACConfiguration = *pBuffer++;
pDMACReg->DMACSync = *pBuffer++;
pDMACReg->DMACC0SrcAddr = *pBuffer++;
pDMACReg->DMACC0DestAddr = *pBuffer++;
pDMACReg->DMACC0LLI = *pBuffer++;
pDMACReg->DMACC0Control0 = *pBuffer++;
pDMACReg->DMACC0Control1 = *pBuffer++;
pDMACReg->DMACC0Configuration = *pBuffer++;
pDMACReg->DMACC1SrcAddr = *pBuffer++;
pDMACReg->DMACC1DestAddr = *pBuffer++;
pDMACReg->DMACC1LLI = *pBuffer++;
pDMACReg->DMACC1Control0 = *pBuffer++;
pDMACReg->DMACC1Control1 = *pBuffer++;
pDMACReg->DMACC1Configuration = *pBuffer++;
pDMACReg->DMACC2SrcAddr = *pBuffer++;
pDMACReg->DMACC2DestAddr = *pBuffer++;
pDMACReg->DMACC2LLI = *pBuffer++;
pDMACReg->DMACC2Control0 = *pBuffer++;
pDMACReg->DMACC2Control1 = *pBuffer++;
pDMACReg->DMACC2Configuration = *pBuffer++;
pDMACReg->DMACC3SrcAddr = *pBuffer++;
pDMACReg->DMACC3DestAddr = *pBuffer++;
pDMACReg->DMACC3LLI = *pBuffer++;
pDMACReg->DMACC3Control0 = *pBuffer++;
pDMACReg->DMACC3Control1 = *pBuffer++;
pDMACReg->DMACC3Configuration = *pBuffer++;
pDMACReg->DMACC4SrcAddr = *pBuffer++;
pDMACReg->DMACC4DestAddr = *pBuffer++;
pDMACReg->DMACC4LLI = *pBuffer++;
pDMACReg->DMACC4Control0 = *pBuffer++;
pDMACReg->DMACC4Control1 = *pBuffer++;
pDMACReg->DMACC4Configuration = *pBuffer++;
pDMACReg->DMACC5SrcAddr = *pBuffer++;
pDMACReg->DMACC5DestAddr = *pBuffer++;
pDMACReg->DMACC5LLI = *pBuffer++;
pDMACReg->DMACC5Control0 = *pBuffer++;
pDMACReg->DMACC5Control1 = *pBuffer++;
pDMACReg->DMACC5Configuration = *pBuffer++;
pDMACReg->DMACC6SrcAddr = *pBuffer++;
pDMACReg->DMACC6DestAddr = *pBuffer++;
pDMACReg->DMACC6LLI = *pBuffer++;
pDMACReg->DMACC6Control0 = *pBuffer++;
pDMACReg->DMACC6Control1 = *pBuffer++;
pDMACReg->DMACC6Configuration = *pBuffer++;
pDMACReg->DMACC7SrcAddr = *pBuffer++;
pDMACReg->DMACC7DestAddr = *pBuffer++;
pDMACReg->DMACC7LLI = *pBuffer++;
pDMACReg->DMACC7Control0 = *pBuffer++;
pDMACReg->DMACC7Control1 = *pBuffer++;
pDMACReg->DMACC7Configuration = *pBuffer++;
}
#if (CPU_NAME == S3C6410)
//--------------------------------------------------------------------
//48MHz clock source for usb host1.1, IrDA, hsmmc, spi is shared with otg phy clock.
//So, initialization and reset of otg phy shoud be done on initial booting time.
//--------------------------------------------------------------------
static void InitializeOTGCLK(void)
{
volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
volatile OTG_PHY_REG *pOtgPhyReg = (OTG_PHY_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_USBOTG_PHY, FALSE);
pSysConReg->HCLK_GATE |= (1<<20);
pSysConReg->OTHERS |= (1<<16);
pOtgPhyReg->OPHYPWR = 0x0; // OTG block, & Analog bock in PHY2.0 power up, normal operation
pOtgPhyReg->OPHYCLK = 0x20; // Externel clock/oscillator, 48MHz reference clock for PLL
pOtgPhyReg->ORSTCON = 0x1;
Delay(100);
pOtgPhyReg->ORSTCON = 0x0;
Delay(100); //10000
pSysConReg->HCLK_GATE &= ~(1<<20);
}
#endif
static VOID S3C6410_SaveState_ONENANDCon(void *pONENANDC, UINT32 *pBuffer)
{
volatile S3C6410_ONENANDCON_REG *pONENANDReg;
pONENANDReg = (S3C6410_ONENANDCON_REG *)pONENANDC;
*pBuffer++ = pONENANDReg->MEM_CFG ; // 0x000
*pBuffer++ = pONENANDReg->BURST_LEN ; // 0x010
*pBuffer++ = pONENANDReg->MEM_RESET0 ; // 0x020
*pBuffer++ = pONENANDReg->INT_ERR_STAT ; // 0x030
*pBuffer++ = pONENANDReg->INT_ERR_MASK ; // 0x040
*pBuffer++ = pONENANDReg->INT_ERR_ACK ; // 0x050
*pBuffer++ = pONENANDReg->ECC_ERR_STAT ; // 0x060
//UINT32 MANUFACT_ID ; // 0x070
//UINT32 DEVICE_ID ; // 0x080
//UINT32 DATA_BUF_SIZE ; // 0x090
//UINT32 BOOT_BUF_SIZE ; // 0x0A0
//UINT32 BUF_AMOUNT ; // 0x0B0
//UINT32 TECH ; // 0x0C0
*pBuffer++ = pONENANDReg->FBA_WIDTH ; // 0x0D0
*pBuffer++ = pONENANDReg->FPA_WIDTH ; // 0x0E0
*pBuffer++ = pONENANDReg->FSA_WIDTH ; // 0x0F0
//UINT32 REVISION ; // 0x100
*pBuffer++ = pONENANDReg->DATARAM0 ; // 0x110
*pBuffer++ = pONENANDReg->DATARAM1 ; // 0x120
//UINT32 SYNC_MODE ; // 0x130
*pBuffer++ = pONENANDReg->TRANS_SPARE ; // 0x140
//UINT32 LOCK_BIT ; // 0x150
*pBuffer++ = pONENANDReg->DBS_DFS_WIDTH ; // 0x160
//UINT32 PAGE_CNT ; // 0x170
//UINT32 ERR_PAGE_ADDR ; // 0x180
//UINT32 BURST_RD_LAT ; // 0x190
*pBuffer++ = pONENANDReg->INT_PIN_ENABLE ; // 0x1A0
*pBuffer++ = pONENANDReg->INT_MON_CYC ; // 0x1B0
*pBuffer++ = pONENANDReg->ACC_CLOCK ; // 0x1C0
*pBuffer++ = pONENANDReg->SLOW_RD_PATH ; // 0x1D0
//UINT32 ERR_BLK_ADDR ; // 0x1E0
//UINT32 FLASH_VER_ID ; // 0x1F0
}
static VOID S3C6410_RestoreState_ONENANDCon(void *pONENANDC, UINT32 *pBuffer)
{
volatile S3C6410_ONENANDCON_REG *pONENANDReg;
pONENANDReg = (S3C6410_ONENANDCON_REG *)pONENANDC;
pONENANDReg->MEM_CFG = *pBuffer++ ; // 0x000
pONENANDReg->BURST_LEN = *pBuffer++ ; // 0x010
pONENANDReg->MEM_RESET0 = *pBuffer++ ; // 0x020
pONENANDReg->INT_ERR_STAT = *pBuffer++ ; // 0x030
pONENANDReg->INT_ERR_MASK = *pBuffer++ ; // 0x040
pONENANDReg->INT_ERR_ACK = *pBuffer++ ; // 0x050
pONENANDReg->ECC_ERR_STAT = *pBuffer++ ; // 0x060
//UINT32 MANUFACT_ID ; // 0x070
//UINT32 DEVICE_ID ; // 0x080
//UINT32 DATA_BUF_SIZE ; // 0x090
//UINT32 BOOT_BUF_SIZE ; // 0x0A0
//UINT32 BUF_AMOUNT ; // 0x0B0
//UINT32 TECH ; // 0x0C0
pONENANDReg->FBA_WIDTH = *pBuffer++ ; // 0x0D0
pONENANDReg->FPA_WIDTH = *pBuffer++ ; // 0x0E0
pONENANDReg->FSA_WIDTH = *pBuffer++ ; // 0x0F0
//UINT32 REVISION ; // 0x100
pONENANDReg->DATARAM0 = *pBuffer++ ; // 0x110
pONENANDReg->DATARAM1 = *pBuffer++ ; // 0x120
//UINT32 SYNC_MODE ; // 0x130
pONENANDReg->TRANS_SPARE = *pBuffer++ ; // 0x140
//UINT32 LOCK_BIT ; // 0x150
pONENANDReg->DBS_DFS_WIDTH = *pBuffer++ ; // 0x160
//UINT32 PAGE_CNT ; // 0x170
//UINT32 ERR_PAGE_ADDR ; // 0x180
//UINT32 BURST_RD_LAT ; // 0x190
pONENANDReg->INT_PIN_ENABLE = *pBuffer++ ; // 0x1A0
pONENANDReg->INT_MON_CYC = *pBuffer++ ; // 0x1B0
pONENANDReg->ACC_CLOCK = *pBuffer++ ; // 0x1C0
pONENANDReg->SLOW_RD_PATH = *pBuffer++ ; // 0x1D0
//UINT32 ERR_BLK_ADDR ; // 0x1E0
//UINT32 FLASH_VER_ID ; // 0x1F0
}
//------------------------------------------------------------------------------
//
// Function: OEMPowerOff
//
// Description: Called when the system is to transition to it's lowest power mode (off)
//
//
void OEMPowerOff()
{
volatile S3C6410_SYSCON_REG *pSysConReg;
volatile S3C6410_GPIO_REG *pGPIOReg;
volatile S3C6410_VIC_REG *pVIC0Reg;
volatile S3C6410_VIC_REG *pVIC1Reg;
volatile S3C6410_DMAC_REG *pDMAC0Reg;
volatile S3C6410_DMAC_REG *pDMAC1Reg;
volatile S3C6410_DMAC_REG *pSDMAC0Reg;
volatile S3C6410_ONENANDCON_REG *pONENAND0Reg;
volatile S3C6410_ONENANDCON_REG *pONENAND1Reg;
#if (CPU_NAME == S3C6410)
volatile OTG_PHY_REG *pOtgPhyReg;
#endif
int nIndex = 0;
OALMSG(TRUE, (L"[OEM] ++OEMPowerOff()\r\n"));
#if 0 // KITL can not support Sleep
// Make sure that KITL is powered off
pArgs = (OAL_KITL_ARGS*)OALArgsQuery(OAL_ARGS_QUERY_KITL);
if ((pArgs->flags & OAL_KITL_FLAGS_ENABLED) != 0)
{
OALKitlPowerOff();
OALMSG(1, (L"OEMPowerOff: KITL Disabled\r\n"));
}
#endif
//-----------------------------
// Disable DVS and Set to Full Speed
//-----------------------------
#ifdef DVS_EN
ChangeDVSLevel(SYS_L0);
#endif
//-----------------------------
// Prepare Specific Actions for Sleep
//-----------------------------
BSPPowerOff();
//------------------------------
// Prepare CPU Entering Sleep Mode
//------------------------------
//----------------
// Map SFR Address
//----------------
pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
pGPIOReg = (S3C6410_GPIO_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_GPIO, FALSE);
pVIC0Reg = (S3C6410_VIC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_VIC0, FALSE);
pVIC1Reg = (S3C6410_VIC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_VIC1, FALSE);
pDMAC0Reg = (S3C6410_DMAC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_DMA0, FALSE);
pDMAC1Reg = (S3C6410_DMAC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_DMA1, FALSE);
pSDMAC0Reg = (S3C6410_DMAC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SDMA0, FALSE);
pONENAND0Reg = (S3C6410_ONENANDCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_ONENANDCON0, FALSE);
pONENAND1Reg = (S3C6410_ONENANDCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_ONENANDCON1, FALSE);
#if (CPU_NAME == S3C6410)
pOtgPhyReg = (OTG_PHY_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_USBOTG_PHY, FALSE);
#endif
//------------------
// Save VIC Registers
//------------------
S3C6410_SaveState_VIC((void *)pVIC0Reg, (void *)pVIC1Reg, g_aSleepSave_VIC);
// Disable All Interrupt
pVIC0Reg->VICINTENCLEAR = 0xFFFFFFFF;
pVIC1Reg->VICINTENCLEAR = 0xFFFFFFFF;
pVIC0Reg->VICSOFTINTCLEAR = 0xFFFFFFFF;
pVIC1Reg->VICSOFTINTCLEAR = 0xFFFFFFFF;
//--------------------
// Save DMAC Registers
//--------------------
S3C6410_SaveState_DMACon((void *)pDMAC0Reg, g_aSleepSave_DMACon0);
S3C6410_SaveState_DMACon((void *)pDMAC1Reg, g_aSleepSave_DMACon1);
S3C6410_SaveState_DMACon((void *)pSDMAC0Reg, g_aSleepSave_SDMACon0);
//------------------------
// Save ONENANDC Registers
//------------------------
S3C6410_SaveState_ONENANDCon((void *)pONENAND0Reg, g_aSleepSave_ONENANDCon0);
S3C6410_SaveState_ONENANDCon((void *)pONENAND1Reg, g_aSleepSave_ONENANDCon1);
//------------------
// Save GPIO Register
//------------------
S3C6410_SaveState_GPIO((void *)pGPIOReg, g_aSleepSave_GPIO);
//--------------------
// Save SysCon Register
//--------------------
S3C6410_SaveState_SysCon((void *)pSysConReg, g_aSleepSave_SysCon);
//-------------------------------------------------------
// Unmask Clock Gating and Block Power turn On (SW workaround)
//-------------------------------------------------------
// HCLK_IROM, HCLK_MEM1, HCLK_MEM0, HCLK_MFC Should be Always On for power Mode (Something coupled with BUS operation)
//pSysConReg->HCLK_GATE |= ((1<<25)|(1<<22)|(1<<21)|(1<<0));
pSysConReg->HCLK_GATE = 0xFFFFFFFF;
pSysConReg->PCLK_GATE = 0xFFFFFFFF;
pSysConReg->SCLK_GATE = 0xFFFFFFFF;
// Turn On All Block Block Power
pSysConReg->NORMAL_CFG = 0xFFFFFF00;
// Wait for Block Power Stable
while((pSysConReg->BLK_PWR_STAT & 0x7E) != 0x7E);
//----------------------------
// Wake Up Source Configuration
//----------------------------
S3C6410_WakeUpSource_Configure();
//-------------------------------
// Extra work for Entering Sleep Mode
//-------------------------------
// USB Power Control
pSysConReg->OTHERS &= ~(1<<16); // USB Signal Mask Clear
pGPIOReg->SPCON |= (1<<3); // USB Tranceiver PAD to Suspend
// TODO: SPCONSLP ???
//pGPIOReg->SPCONSLP; // Use Default Valie
//-------------------------------
// GPIO Configuration for Sleep State
//-------------------------------
// TODO: Configure GPIO at Sleep
//BSPConfigGPIOforPowerOff();
// Sleep Mode Pad Configuration
pGPIOReg->SLPEN = 0x2; // Controlled by SLPEN Bit (You Should Clear SLPEN Bit in Wake Up Process...)
//-----------------------
// CPU Entering Sleep Mode
//-----------------------
OALCPUPowerOff(); // Now in Sleep
//----------------------------
// CPU Wake Up from Sleep Mode
//----------------------------
//----------------------------
// Wake Up Source Determine
//----------------------------
S3C6410_WakeUpSource_Detect();
// USB Power Control
#if (CPU_NAME == S3C6410)
InitializeOTGCLK(); // pll_powerdown, suspend mode
#endif
#if (CPU_NAME == S3C6400)
pSysConReg->OTHERS |= (1<<16); // TODO: USB Signal Mask Set (Device must handle it...)
#endif
pGPIOReg->SPCON &= ~(1<<3); // USB Tranceiver PAD to Normal
// Restore SysCon Register
S3C6410_RestoreState_SysCon((void *)pSysConReg, g_aSleepSave_SysCon);
// Restore GPIO Register
S3C6410_RestoreState_GPIO((void *)pGPIOReg, g_aSleepSave_GPIO);
// Sleep Mode Pad Configuration
pGPIOReg->SLPEN = 0x2; // Clear SLPEN Bit for Pad back to Normal Mode
//---------------------------
// Restore ONENANDC Registers
//---------------------------
S3C6410_RestoreState_ONENANDCon((void *)pONENAND0Reg, g_aSleepSave_ONENANDCon0);
S3C6410_RestoreState_ONENANDCon((void *)pONENAND1Reg, g_aSleepSave_ONENANDCon1);
//-----------------------
// Restore DMAC Registers
//-----------------------
S3C6410_RestoreState_DMACon((void *)pDMAC0Reg, g_aSleepSave_DMACon0);
S3C6410_RestoreState_DMACon((void *)pDMAC1Reg, g_aSleepSave_DMACon1);
S3C6410_RestoreState_DMACon((void *)pSDMAC0Reg, g_aSleepSave_SDMACon0);
// Restore VIC Registers
S3C6410_RestoreState_VIC((void *)pVIC0Reg, (void *)pVIC1Reg, g_aSleepSave_VIC);
//pVIC0Reg->VICADDRESS = 0x0;
//pVIC1Reg->VICADDRESS = 0x0;
// UART Debug Port Initialize
OEMInitDebugSerial();
// Disable Vectored Interrupt Mode on CP15
System_DisableVIC();
// Enable Branch Prediction on CP15
System_EnableBP();
// Enable IRQ Interrupt on CP15
System_EnableIRQ();
// Enable FIQ Interrupt on CP15
System_EnableFIQ();
if (g_oalWakeSource == SYSWAKE_UNKNOWN)
{
OALMSG(TRUE, (L"[OEM:ERR] OEMPowerOff() : SYSWAKE_UNKNOWN , WAKEUP_STAT = 0x%08x", g_LastWakeupStatus));
}
// Initialize System Timer
OEMInitializeSystemTimer(RESCHED_PERIOD, OEM_COUNT_1MS, 0);
#if 0 // KITL can not support Sleep
// Reinitialize KITL
if ((pArgs->flags & OAL_KITL_FLAGS_ENABLED) != 0)
{
OALKitlPowerOn();
}
#endif
//--------------------------------------
// Post Processing Specific Actions for Wake Up
//--------------------------------------
BSPPowerOn();
OALMSG(TRUE, (L"[OEM] --OEMPowerOff()\r\n"));
}
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