s3c6410_system.s

SAMSUNG S3C6410 CPU BSP for winmobile6

;------------------------------------------------------------------------------
;
;  Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
;  Use of this source code is subject to the terms of the Microsoft end-user
;  license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
;  If you did not accept the terms of the EULA, you are not authorized to use
;  this source code. For a copy of the EULA, please see the LICENSE.RTF on your
;  install media.
;
;------------------------------------------------------------------------------
;
;   File:  startup.s
;
;   Kernel startup routine for Samsung SMDK6410 board. Hardware is
;   initialized in boot loader - so there isn't much code at all.
;
;------------------------------------------------------------------------------

		INCLUDE kxarm.h
		INCLUDE armmacros.s
		INCLUDE s3c6410.inc

		TEXTAREA

		EXPORT	System_EnableVIC
		EXPORT	System_DisableVIC
		EXPORT	System_EnableIRQ
		EXPORT	System_DisableIRQ
		EXPORT	System_EnableFIQ
		EXPORT	System_DisableFIQ
		EXPORT	System_EnableBP
		EXPORT	System_DisableBP
		EXPORT	System_EnableICache
		EXPORT	System_SetSyncMode
		EXPORT	System_SetAsyncMode
		EXPORT	System_WaitForInterrupt


	;--------------------
	;	Enable VIC
	;--------------------
	LEAF_ENTRY System_EnableVIC
		mrc		p15,0,r0,c1,c0,0
		orr		r0,r0,#R1_VE
		mcr		p15,0,r0,c1,c0,0
		mov		pc, lr
		ENTRY_END


	;--------------------
	;	Disable VIC
	;--------------------
	LEAF_ENTRY System_DisableVIC
		mrc		p15,0,r0,c1,c0,0
		bic		r0,r0,#R1_VE
		mcr		p15,0,r0,c1,c0,0
		mov		pc, lr
		ENTRY_END


	;--------------------
	;	Enable IRQ
	;--------------------
	LEAF_ENTRY System_EnableIRQ
		mrs		r0,cpsr
		bic		r0,r0,#I_Bit
		msr		cpsr_cxsf,r0
		mov		pc, lr
		ENTRY_END


	;--------------------
	;	Disable IRQ
	;--------------------
	LEAF_ENTRY System_DisableIRQ
		mrs		r0,cpsr
		orr		r0,r0,#I_Bit
		msr		cpsr_cxsf,r0
		mov		pc, lr
		ENTRY_END


	;--------------------
	;	Enable FIQ
	;--------------------
	LEAF_ENTRY System_EnableFIQ
		mrs		r0,cpsr
		bic		r0,r0,#F_Bit
		msr		cpsr_cxsf,r0
		mov		pc, lr
		ENTRY_END


	;--------------------
	;	Disable FIQ
	;--------------------
	LEAF_ENTRY System_DisableFIQ
		mrs		r0,cpsr
		orr		r0,r0,#F_Bit
		msr		cpsr_cxsf,r0
		mov		pc, lr
		ENTRY_END


	;-------------------------
	;	Enable Branch Prediction
	;-------------------------
	LEAF_ENTRY System_EnableBP
		mrc		p15,0,r0,c1,c0,0
		orr		r0,r0,#R1_BP
		mcr		p15,0,r0,c1,c0,0
		mov		pc, lr
		ENTRY_END


	;-------------------------
	;	Disable Branch Prediction
	;-------------------------
	LEAF_ENTRY System_DisableBP
		mrc		p15,0,r0,c1,c0,0
		bic		r0,r0,#R1_BP
		mcr		p15,0,r0,c1,c0,0
		mov		pc, lr
		ENTRY_END


	;-------------------------
	;	Enable ICache
	;-------------------------
	LEAF_ENTRY System_EnableICache
		mrc		p15, 0, r0, c1, c0, 0
		orr		r0, r0, #R1_I
		mcr		p15, 0, r0, c1, c0, 0
		mov		pc, lr
		ENTRY_END


	;---------------------------
	;	Set to Synchronous Mode
	;---------------------------
	LEAF_ENTRY System_SetSyncMode

		ldr		r0, =OTHERS
		ldr		r1, [r0]
		orr		r1, r1, #0x40			; SyncMUX = Sync
		str		r1, [r0]

		nop
		nop
		nop
		nop
		nop

		ldr		r1, [r0]
		orr		r1, r1, #0x80			; SyncReq = Sync
		str		r1, [r0]

WaitForSync
		ldr		r1, [r0]				; Read OTHERS
		and		r1, r1, #0xF00			; Wait SYNCMODEACK = 0xF
		cmp		r1, #0xF00
		bne		WaitForSync

		mov		pc, lr

		ENTRY_END


	;---------------------------
	;	Set to Asynchronous Mode
	;---------------------------
	LEAF_ENTRY System_SetAsyncMode

		ldr		r0, =OTHERS
		ldr		r1, [r0]
		bic		r1, r1, #0xC0
		orr		r1, r1, #0x40			; SyncReq = Async, SyncMUX = Sync
		str		r1, [r0]

WaitForAsync
		ldr		r1, [r0]				; Read OTHERS
		and		r1, r1, #0xF00			; Wait SYNCMODEACK = 0x0
		cmp		r1, #0x0
		bne		WaitForAsync

		ldr		r0, =OTHERS
		ldr		r1, [r0]
		bic		r1, r1, #0x40			; SyncMUX = Async
		str		r1, [r0]

		nop
		nop
		nop
		nop
		nop

		mov		pc, lr

		ENTRY_END


	;---------------------------
	;	Set WaitForInterrupt
	;---------------------------
	LEAF_ENTRY System_WaitForInterrupt

		mov		r0, #0

		mcr		p15,0,r0,c7,c10,4		; Data Synchronization Barrier (TRM said...)
		mcr		p15,0,r0,c7,c0,4		; Wait For Interrupt

		mov		pc, lr

		ENTRY_END


		END

;------------------------------------------------------------------------------