startup.s

来自「SAMSUNG S3C6410 CPU BSP for winmobile6」· S 代码 · 共 487 行

;------------------------------------------------------------------------------
;
;  Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
;  Use of this source code is subject to the terms of the Microsoft end-user
;  license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
;  If you did not accept the terms of the EULA, you are not authorized to use
;  this source code. For a copy of the EULA, please see the LICENSE.RTF on your
;  install media.
;
;------------------------------------------------------------------------------
;
;   File:  startup.s
;
;   Hardware startup routine for Samsung SMDK6410 board.
;
;------------------------------------------------------------------------------

		INCLUDE	kxarm.h
		INCLUDE	s3c6410.inc
		INCLUDE	image_cfg.inc
	[	POP_OPTION = POP_NONE
		INCLUDE MemParam_mDDR.inc
	]
	[	POP_OPTION = POP_X5A
		INCLUDE MemParam_X5A.inc
	]

DRAM_BaseAddress	EQU		(0x50000000)
ONENAND_BaseAddress EQU		(0x70100000)
ONENAND_ReadBase	EQU		(0x01000000)	;6410 Base Map01 command
DownloadAddress		EQU		(DRAM_BaseAddress+0x01300000)

ONBL2_START_BLOCK	EQU		(0)
ONBL2_START_PAGE	EQU		(2)
ONBL2_END_PAGE		EQU		(63)

		IMPORT	main					; C entrypoint for Steppingstone loader.

		STARTUPTEXT

;------------------------------------------------------------------------------
;
;	StartUp Entry
;
;	Main entry point for CPU initialization.
;
;------------------------------------------------------------------------------

	LEAF_ENTRY	StartUp

		b		ResetHandler
		b		.				; HandlerUndef	(0x00000004)
		b		.				; HandlerSWI		(0x00000008)
		b		.				; HandlerPabort	(0x0000000C)
		b		.				; HandlerDabort	(0x00000010)
		b		.				; HandlerReserved	(0x00000014)
		b		.				; HandlerIRQ		(0x00000018)
		b		.				; HandlerFIQ		(0x0000001C)

;------------------------------------------------------------------------------
;	End of StartUp
;------------------------------------------------------------------------------


;------------------------------------------------------------------------------
;
;	ResetHandler Function
;
;	Reset Exception Handler
;
;------------------------------------------------------------------------------

ResetHandler

;------------------------------------
;	Enable Instruction Cache
;------------------------------------

		mov		r0, #0
		mcr		p15, 0, r0, c7, c7, 0			; Invalidate Entire I&D Cache

		mrc		p15, 0, r0, c1, c0, 0			; Enable I Cache
		orr		r0, r0, #R1_I
		mcr		p15, 0, r0, c1, c0, 0

;------------------------------------
;	Peripheral Port Setup
;------------------------------------

		ldr		r0, =0x70000013		; Base Addres : 0x70000000, Size : 256 MB (0x13)
		mcr		p15,0,r0,c15,c2,4

;------------------------------------
;	Disable WatchDog Timer
;------------------------------------

		ldr		r0, =WTCON
		ldr		r1, =0x0
		str		r1, [r0]

;--------------------------------------------
;    Memport1 drive strength change 3mA->7mA
;--------------------------------------------
	
		ldr 	r3, =MEM1DRVCON
		ldr 	r4, =0xaaaaaaaa
		str 	r4, [r3]

		ldr 	r3, =MEM0DRVCON
		ldr 	r4, =0xaaaaaaaa
		str 	r4, [r3]
	

;------------------------------------
;	Change PLL Value
;------------------------------------

	[  SYNCMODE								; Operating Mode Change
		ldr		r0, =OTHERS
		ldr		r1, [r0]
		mov		r2, #0x40				; OTHERS[6] = "1"
		orr		r1,	r1, r2
		str		r1,	[r0]				; SYNCMUXSEL
				
		;DELAY
		NOP
		NOP
		NOP
		NOP
		NOP
				
		ldr		r2, =((1<<7))			; SYNCMODE, 			
		orr		r1,	r1, r2
		str		r1, [r0]				; Assert SYNCACK, VICSYNCEN
				
Check_SYNCACK
		ldr		r1, [r0]
		ldr		r2, =(0xF<<8)
		and		r1, r1, r2				; OTHERS[11:8]
		cmp		r1, #0xF00
		bne		Check_SYNCACK			
	]	

		ldr		r1, =0x4b1      ; Lock Time Value, Fin=12MHz - 0x4B1(min)
		ldr		r2, =0xe13			; Lock Time : 0xe13 (300us @Fin12MHz) for EPLL

		ldr		r0, =APLL_LOCK		; APLL Lock Time
		str		r1, [r0]
		str		r1, [r0, #0x4]			; MPLL Lock Time
		str		r2, [r0, #0x8]			; EPLL Lock Time

		ldr		r1,	[r0,#0x20]			; Load Clock Divider Value
		bic		r1, r1, #0x30000
		bic		r1, r1, #0xff00
		bic		r1, r1, #0xff
		ldr		r2, =((PCLK_DIV<<12)+(HCLKx2_DIV<<9)+(HCLK_DIV<<8)+(MPLL_DIV<<4)+(APLL_DIV<<0))
		orr		r1, r1, r2			
		str		r1,	[r0,#0x20]			; CLK_DIV0 Register

		ldr		r1, =((1<<31)+(APLL_MVAL<<16)+(APLL_PVAL<<8)+(APLL_SVAL))
		str		r1, [r0, #0xC]			; APLL_CON

		ldr		r1, =((1<<31)+(MPLL_MVAL<<16)+(MPLL_PVAL<<8)+(MPLL_SVAL))
		str		r1, [r0, #0x10]			; MPLL_CON
		
		ldr		r1, =EPLL_KVAL
		str		r1, [r0, #0x18]			; EPLL_CON1

		ldr		r1, =((1<<31)+(EPLL_MVAL<<16)+(EPLL_PVAL<<8)+(EPLL_SVAL))
		str		r1, [r0, #0x14]			; EPLL_CON0

;------------------------------------
;	Enable PLL Clock Out
;------------------------------------

		ldr		r0, =CLK_SRC
		ldr		r1, [r0]
		orr		r1, r1, #0x7			; PLL  Clockout
		str		r1, [r0]				; System will be waiting for PLL unlocked after this instruction

;------------------------------------
;	OneNAND Setting
;------------------------------------
		ldr		r0, =ONENAND_BaseAddress
		ldr		r1, =0x40e0
		str		r1, [r0]
						
		mov		r0,	#0x00000000			; bootram region in OneNAND
		mov		r1,	#0x0C000000			; steppingstone region

boot_to_step
		ldmia	r0!, {r4-r7,r9-r12}
		stmia	r1!, {r4-r7,r9-r12}		; Copy the image from DataBuffer0 into Stepping Stone.

		cmp		r0, #0x400
		bne		boot_to_step

		add		pc, pc, #0x0c000000

stepping_stone
		nop
;------------------------------------
;	Expand Memory Port 1 to x32
;------------------------------------

		ldr		r0, =MEM_SYS_CFG
		ldr		r1, [r0]
		bic		r1, r1, #0x80			; ADDR_EXPAND to "0"
		str		r1, [r0]

;------------------------------------
;	Initialize Dynamic Memory Controller
;------------------------------------

		bl		InitDMC


;------------------------------------
;	Power Management Routine
;	(WakeUp Processing)
;------------------------------------

		ldr		r0, =RST_STAT
		ldr		r1, [r0]
		and		r1, r1, #0x3F
		cmp		r1, #0x8
		bne		Normal_Boot_Sequence			; Normal Booting (Not Wake Up)

		ldr		r0, =DRAM_BASE_PA_START	; DRAM Base Physical Address
		add		r0, r0, #IMAGE_NK_OFFSET		; NK Offset in DRAM
		mov		pc, r0						; Jump to StartUp address
		b		.

Normal_Boot_Sequence

;------------------------------------
;	Clear DRAM
;------------------------------------

    [ {FALSE}
		mov		r1, #0
		mov 	r2, #0
		mov 	r3, #0
		mov 	r4, #0
		mov 	r5, #0
		mov 	r6, #0
		mov 	r7, #0
		mov 	r8, #0

		ldr		r0, =DRAM_BASE_PA_START	; Start address (Physical 0x5000.0000)
		ldr		r9, =DRAM_SIZE				; 128 MB of RAM
10
		stmia	r0!, {r1-r8}
		subs		r9, r9, #32
		bne		%B10
	]

		ldr		r7, =DownloadAddress		; Address to download
		mov		r4, #ONBL2_START_BLOCK					; Block Number....................rb1004
		mov		r3, #ONBL2_START_PAGE					; Page Number

page_increment	
		;nop		
		;b 		page_increment

		ldr		r2, =ONENAND_ReadBase	; Map01 command base address
		add		r2, r2, r4, LSL #12		; Block Address Setting....................rb1004				
		mov		r8, #0x80				; Count to move (0x80*4burst*4byte = 2KB)
		add		r3, r3, #1				; Increment the Page Number
		add		r2, r2, r3, LSL #6			; Address to load data
move_page				
		ldmia	r2, {r9-r12}				; 
		stmia	r7!, {r9-r12}			; 
		subs	r8, r8, #0x1				; Count decrement
		bne		move_page 


		ldr		r0, =0x70100000
int_wait	
;		ldr		r1, [r0, #0x30]
;		tst		r1, #0x400				; check the INT_ACT bit of OneNand INT_ERR_STAT register
;		beq		int_wait
		mov		r1, #0x400
		str		r1, [r0, #0x50]				; clear the INT_ACT bit

		cmp		r3, #63					; Repeat movement to page number 63 (126KB)
		blt		page_increment

		add		r4, r4, #1				; Block Number Increment...............rb1004
		mov		r3, #0xFFFFFFFF			; .....................rb1004
		cmp		r4, #1					; Block Size Number....................rb1004
		blt		page_increment			; .....................rb1004

		ldr		r0, =DownloadAddress
		mov		pc, r0					; Jump to download address


;------------------------------------
;	Jump to Main() "C" Routine
;------------------------------------

		bl		main
		b 		.			; Should not be here...

		ENTRY_END

;------------------------------------------------------------------------------
;
;	InitDMC Function
;
;	Initialize DMC(Dynamic Memory Controller) and DRAM
;
;------------------------------------------------------------------------------

	LEAF_ENTRY InitDMC

;---------------------------
; Initialize DMC (mDDR)
;---------------------------

	[	USE_DMC1

		ldr		r0, =DMC1_BASE					; DMC1 base address

		ldr		r1, =0x4
		str		r1, [r0, #INDEX_MEMCCMD]			; Enter the Config. Mode

	[	DVS_EN
		ldr		r1, =DMC_DDR_REFRESH_PRD_DVS	; Refresh Rate is set to the lowest HCLK frequency when DVS is enabled
	|
		ldr		r1, =DMC_DDR_REFRESH_PRD		; Timing Para.
	]
		str		r1, [r0, #INDEX_REFRESH]
		ldr		r1, =DMC_DDR_CAS_LATENCY
		str		r1, [r0, #INDEX_CASLAT]

		ldr		r1, =DMC_DDR_t_DQSS
		str		r1, [r0, #INDEX_T_DQSS]

		ldr		r1, =DMC_DDR_t_MRD
		str		r1, [r0, #INDEX_T_MRD]

		ldr		r1, =DMC_DDR_t_RAS
		str		r1, [r0, #INDEX_T_RAS]

		ldr		r1, =DMC_DDR_t_RC
		str		r1, [r0, #INDEX_T_RC]

		ldr		r1, =DMC_DDR_t_RCD
		ldr		r2, =DMC_DDR_schedule_RCD
		orr		r1, r1, r2
		str		r1, [r0, #INDEX_T_RCD]

		;ldr		r1, =DMC_DDR_t_RFC
		;ldr		r2, =DMC_DDR_schedule_RFC
		;orr		r1, r1, r2
		ldr		r1, =0xB2
		str		r1, [r0, #INDEX_T_RFC]

		ldr		r1, =DMC_DDR_t_RP
		ldr		r2, =DMC_DDR_schedule_RP
		orr		r1, r1, r2
		str		r1, [r0, #INDEX_T_RP]

		ldr		r1, =DMC_DDR_t_RRD
		str		r1, [r0, #INDEX_T_RRD]

		ldr		r1, =DMC_DDR_t_WR
		str		r1, [r0, #INDEX_T_WR]

		ldr		r1, =DMC_DDR_t_WTR
		str		r1, [r0, #INDEX_T_WTR]

		ldr		r1, =DMC_DDR_t_XP
		str		r1, [r0, #INDEX_T_XP]

		ldr		r1, =DMC_DDR_t_XSR
		str		r1, [r0, #INDEX_T_XSR]

		ldr		r1, =DMC_DDR_t_ESR
		str		r1, [r0, #INDEX_T_ESR]

		ldr		r1, =DMC1_MEM_CFG
		str		r1, [r0, #INDEX_MEMCFG]

		ldr		r1, =DMC1_MEM_CFG2
		str		r1, [r0, #INDEX_MEMCFG2]

	[	USE_DMC1_CHIP0
		ldr		r1, =DMC1_CHIP0_CFG
		str		r1, [r0, #INDEX_CHIP0_CFG]
	]

	[	USE_DMC1_CHIP1
		ldr		r1, =DMC1_CHIP1_CFG
		str		r1, [r0, #INDEX_CHIP1_CFG]
	]

			[{TRUE}
		ldr		r1, =DMC1_USER_CFG
		str		r1, [r0, #INDEX_USER_CFG]
			]

	;---------------------------------------------
	; DMC1 DDR Chip 0 configuration direct command reg
	;---------------------------------------------
	[	USE_DMC1_CHIP0

		; DMC1 DDR Chip 0 configuration direct command reg
		; NOP
		ldr		r1, =DMC_NOP0
		str		r1, [r0, #INDEX_DIRECTCMD]

		; Precharge All
		ldr		r1, =DMC_PA0
		str		r1, [r0, #INDEX_DIRECTCMD]

		; Auto Refresh	2 time
		ldr		r1, =DMC_AR0
		str		r1, [r0, #INDEX_DIRECTCMD]
		str		r1, [r0, #INDEX_DIRECTCMD]

		; Mode Reg (MRS, CAS3, BL4)
		ldr		r1, =DMC_mDDR_MR0
		str		r1, [r0, #INDEX_DIRECTCMD]

		; EMRS
		ldr		r1, =DMC_mDDR_EMR0			; DS:Full, PASR:Full Array
		str		r1, [r0, #INDEX_DIRECTCMD]


	] ; USE_DMC1_CHIP0

	;---------------------------------------------
	; DMC1 DDR Chip 1 configuration direct command reg
	;---------------------------------------------
	[	USE_DMC1_CHIP1

		; DMC1 DDR Chip 1 configuration direct command reg
		; NOP
		ldr		r1, =DMC_NOP1
		str		r1, [r0, #INDEX_DIRECTCMD]

		; Precharge All
		ldr		r1, =DMC_PA1
		str		r1, [r0, #INDEX_DIRECTCMD]

		; Auto Refresh	2 time
		ldr		r1, =DMC_AR1
		str		r1, [r0, #INDEX_DIRECTCMD]
		str		r1, [r0, #INDEX_DIRECTCMD]

		; EMRS
		ldr		r1, =DMC_mDDR_EMR1			; DS:Full, PASR:Full Array
		str		r1, [r0, #INDEX_DIRECTCMD]

		; Mode Reg (MRS, CAS3, BL4)
		ldr		r1, =DMC_mDDR_MR1
		str		r1, [r0, #INDEX_DIRECTCMD]

	] ; USE_DMC1_CHIP1

		; Enable DMC1
		mov		r1, #0x0
		str		r1, [r0, #INDEX_MEMCCMD]

Wait_for_DMC1Ready

		ldr		r1, [r0, #INDEX_MEMSTAT]
		mov		r2, #0x3
		and		r1, r1, r2
		cmp		r1, #0x1
		bne		Wait_for_DMC1Ready

	] ; USE_DMC1

		NOP

		mov 	pc, lr

		ENTRY_END

		END