startup.s

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;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;------------------------------------------------------------------------------
;
;   File:  startup.s
;
;   Kernel startup routine for Samsung SMDK6410 board. Hardware is
;   initialized in boot loader - so there isn't much code at all.
;
;------------------------------------------------------------------------------

		INCLUDE kxarm.h
		INCLUDE armmacros.s
		INCLUDE s3c6410.inc
		INCLUDE	image_cfg.inc

		IMPORT	OALClearUTLB
		IMPORT	OALFlushICache
		IMPORT	OALFlushDCache

		IMPORT	System_DisableVIC
		IMPORT	System_EnableIRQ
		IMPORT	System_SetSyncMode
		IMPORT	System_SetAsyncMode

;-------------------------------------------------------------------------------
;	Definition for MMU table initialization
;-------------------------------------------------------------------------------

PHYBASE		EQU		0x50000000	  ; Physical DRAM Base Address
PTs			EQU		0x50010000	  ; 1st level Page Table Base Address (PHYBASE + 0x10000) save room for interrupt vectors
BANK_SHIFT	EQU		20

RAM_CB      EQU     (PHYBASE + 0x00000040E)
RAM_NCNB    EQU     (PHYBASE + 0x000000402)

PTR_1ST_PTE EQU     (PHYBASE >> 18)  ;;(0x5000 / 4)

;------------------------------------------------------------------------------
; Data Cache Characteristics.
;
DCACHE_LINES_PER_SET_BITS       EQU     2
DCACHE_LINES_PER_SET            EQU     4
DCACHE_NUM_SETS                 EQU     128
DCACHE_SET_INDEX_BIT            EQU     (32 - DCACHE_LINES_PER_SET_BITS)
DCACHE_LINE_SIZE                EQU     32



;------------------------------------------------------------------------------
; Sleep state constants
;
; Location of sleep data

; BUGBUG - this needs to be declared as a local var.

SLEEPDATA_BASE_PHYSICAL	 EQU     0x50020800



;------------------------------------------------------------------------------
;
;	Macro for LED on SMDK Board (GPN[15:12])
;
;	LED_ON for physical address domain
;	VLED_ON for virtual address domain
;
;------------------------------------------------------------------------------

	MACRO

		LED_ON	$data

		ldr		r10, =GPNPUD
		ldr		r11, [r10]
		bic		r11, r11, #0xF000	; Pull-Up-Down Disable
		str		r11, [r10]

		ldr		r10, =GPNDAT
		ldr		r11, [r10]
		bic		r11, r11, #0xF000
		ldr		r12, =$data
		mov		r12, r12, lsl #12	; [15:12]
		orr		r11, r11, r12
		str		r11, [r10]

		ldr		r10, =GPNCON
		ldr		r11, [r10]
		bic		r11, r11, #0xFF000000
		orr		r11, r11, #0x55000000	; GPN[15:12] Output .
		str		r11, [r10]

		MEND


	MACRO

		VLED_ON	$data

		ldr		r10, =vGPNPUD
		ldr		r11, [r10]
		bic		r11, r11, #0xF000	; Pull-Up-Down Disable
		str		r11, [r10]

		ldr		r10, =vGPNDAT
		ldr		r11, [r10]
		bic		r11, r11, #0xF000
		ldr		r12, =$data
		mov		r12, r12, lsl #12	; [15:12]
		orr		r11, r11, r12
		str		r11, [r10]

		ldr		r10, =vGPNCON
		ldr		r11, [r10]
		bic		r11, r11, #0xFF000000
		orr		r11, r11, #0x55000000	; GPN[15:12] Output .
		str		r11, [r10]

		MEND

;------------------------------------------------------------------------------
;	End of Macro
;------------------------------------------------------------------------------


		TEXTAREA

		IMPORT  main

		INCLUDE	oemaddrtab_cfg.inc

;------------------------------------------------------------------------------
;
;	StartUp Entry
;
;	Main entry point for CPU initialization.
;
;------------------------------------------------------------------------------
	LEAF_ENTRY      StartUp
	
		b		ResetHandler
		b		.				; HandlerUndef
		b		.				; HandlerSWI
		b		.				; HandlerPabort
		b		.				; HandlerDabort
		b		.				; HandlerReserved
		b		.				; HandlerIRQ
		b		.				; HandlerFIQ

;------------------------------------------------------------------------------
;
;	ResetHandler Function
;
;	Reset Exception Handler
;
;------------------------------------------------------------------------------

ResetHandler

		LED_ON 0x1

;------------------------------------
;	Flush TLB, Invalidate ICache, DCache
;------------------------------------
		mov     r0, #0
		mcr     p15, 0, r0, c8, c7, 0           ; flush both TLB
		mcr     p15, 0, r0, c7, c5, 0           ; invalidate instruction cache
		mcr     p15, 0, r0, c7, c6, 0           ; invalidate data cache

;------------------------------------
;	Peripheral Port Setup
;------------------------------------

		ldr		r0, =0x70000013		; Base Addres : 0x70000000, Size : 256 MB (0x13)
		mcr		p15,0,r0,c15,c2,4


;------------------------------------
;	Interrupt Disable
;------------------------------------

		ldr		r0, =VIC0INTENCLEAR
		ldr		r1, =0xFFFFFFFF;
		str		r1, [r0]

		ldr		r0, =VIC1INTENCLEAR
		ldr		r1, =0xFFFFFFFF;
		str		r1, [r0]

;------------------------------------
;	Disable WatchDog Timer
;------------------------------------

		ldr		r0, =WTCON
		ldr		r1, =0x0
		str		r1, [r0]

;---------------------------------------
;	Configure SMC Chip Select Mux for NAND
;---------------------------------------
;
;		ldr		r0, =MEM_SYS_CFG
;		ldr		r1, [r0]
;		bic		r1, r1, #1000			; Bus Width : 8 bit
;		orr		r1, r1, #0x3			; CS2 -> NFCON CS0
;		str		r1, [r0]

;---------------------------------------
;	USB Signal Mask (for reduce current ???)
;---------------------------------------

	[ {TRUE}
		ldr		r0, =OTHERS
		ldr		r1, [r0]
		bic		r1, r1, #0x10000		; USB_SIG_MASK
		str		r1, [r0]
	]

	[ CHANGE_PLL_CLKDIV_ON_EBOOT

;-----------------------------------------------
;	Change Operation Mode to Sync Mode or Async Mode
;-----------------------------------------------

		ldr		r0, =OTHERS
		ldr		r1, [r0]
		and		r1, r1, #0x40

		cmp		r1, #0x40			; OTHERS[6] = 0:AsyncModde 1:SyncMode
	[ 	CPU_NAME = S3C6410
		[ (SYNCMODE) 
			bne		System_SetSyncMode
		|
			beq		System_SetAsyncMode
		]
	]
	[ 	CPU_NAME = S3C6400
		beq		System_SetAsyncMode
	]

;---------------------------------------
;	Check PLL and CLKDIV
;---------------------------------------

		ldr		r3, =0x83FF3F07		; Mask for APLL_CON/MPLL_CON
		ldr		r4, =0x80FF3F07		; Mask for EPLL_CON0
		ldr		r5, =0x0000FFFF		; Mask for EPLL_CON1
		ldr		r6, =0x0003FF17		; Mask for CLKDIV0

		ldr		r0, =APLL_CON		; Check APLL
		ldr		r1, [r0]
		and		r1, r1, r3
		ldr		r2, =((1<<31)+(APLL_MVAL<<16)+(APLL_PVAL<<8)+(APLL_SVAL))	; APLL_CON value to configure
		cmp		r1, r2
		bne		PLL_NeedToConfigure

		ldr		r0, =MPLL_CON		; Check MPLL
		ldr		r1, [r0]
		and		r1, r1, r3
		ldr		r2, =((1<<31)+(MPLL_MVAL<<16)+(MPLL_PVAL<<8)+(MPLL_SVAL))	; MPLL_CON value to configure
		cmp		r1, r2
		bne		PLL_NeedToConfigure

		ldr		r0, =EPLL_CON0		; Check EPLL_CON0
		ldr		r1, [r0]
		and		r1, r1, r4
		ldr		r2, =((1<<31)+(EPLL_MVAL<<16)+(EPLL_PVAL<<8)+(EPLL_SVAL))		; EPLL_CON0 value to configure
		cmp		r1, r2
		bne		PLL_NeedToConfigure

		ldr		r0, =EPLL_CON1		; Check EPLL_CON1
		ldr		r1, [r0]
		and		r1, r1, r5
		ldr		r2, =EPLL_KVAL		; EPLL_CON1 value to configure
		cmp		r1, r2
		bne		PLL_NeedToConfigure

		ldr		r0, =CLK_DIV0		; Check CLKDIV0
		ldr		r1, [r0]
		and		r1, r1, r6
	[ 	CPU_NAME = S3C6410
		ldr		r2, =((PCLK_DIV<<12)+(HCLKx2_DIV<<9)+(HCLK_DIV<<8)+(MPLL_DIV<<4)+(APLL_DIV<<0))		; CLKDIV0 value to configure
	]
	[ 	CPU_NAME = S3C6400
		ldr		r2, =((OND_DIV<<16)+(PCLK_DIV<<12)+(HCLKx2_DIV<<9)+(HCLK_DIV<<8)+(MPLL_DIV<<4)+(APLL_DIV<<0))		; CLKDIV0 value to configure
	]
		cmp		r1, r2
		bne		CLKDIV_NeedToConfigure

		b		PLL_CLKDIV_AlreadyConfigured	; APLL/MPLL/EPLL and CLKDIV0 is already configured

;------------------------------------
;	Prepare to Change PLL
;------------------------------------

PLL_NeedToConfigure

	[ CPU_NAME = S3C6410

;------------------------------------
;	Disable PLL Clock Out
;------------------------------------

		ldr		r0, =CLK_SRC