s3c6410.inc

来自「SAMSUNG S3C6410 CPU BSP for winmobile6」· INC 代码 · 共 717 行 · 第 1/2 页

S3C6410_ACLK	EQU	(S3C6410_APLL_CLK/(APLL_DIV+1))	; ARMCLK = 1066 MHz

		]	; 1066 MHz		

	]
	; EPLL Fout 96 MHz
	[ S3C6410_ECLK = ECLK_96MHZ

;Fout=96MHz
EPLL_MVAL	EQU	(32)
EPLL_PVAL	EQU	(1)
EPLL_SVAL	EQU	(2)
EPLL_KVAL	EQU	(0)

  	]	; 96 MHz

	; EPLL Fout 84.666667 MHz
	[ S3C6410_ECLK = ECLK_84MHZ

;Fout=84.67MHz
EPLL_MVAL	EQU	(254)
EPLL_PVAL	EQU	(9)
EPLL_SVAL	EQU	(2)
EPLL_KVAL	EQU	(0)

  	]	; 84.666667 MHz

	; EPLL Fout 92,160,000 Hz
	[ S3C6410_ECLK = ECLK_92MHZ

;Fout=92.16MHz
EPLL_MVAL	EQU	(192)
EPLL_PVAL	EQU	(25)
EPLL_SVAL	EQU	(0)
EPLL_KVAL	EQU	(0)

  	]	; 92.16 MHz

;--------------------------------------------------
;  Startup Clock Definition (Same as Normal Clock)
;--------------------------------------------------

Startup_APLL_MVAL	EQU	(APLL_MVAL)
Startup_APLL_PVAL	EQU	(APLL_PVAL)
Startup_APLL_SVAL	EQU	(APLL_SVAL)

Startup_MPLL_MVAL	EQU	(MPLL_MVAL)
Startup_MPLL_PVAL	EQU	(MPLL_PVAL)
Startup_MPLL_SVAL	EQU	(MPLL_SVAL)

Startup_EPLL_MVAL	EQU	(EPLL_MVAL)
Startup_EPLL_PVAL	EQU	(EPLL_PVAL)
Startup_EPLL_SVAL	EQU	(EPLL_SVAL)
Startup_EPLL_KVAL	EQU	(EPLL_KVAL)

Startup_APLL_DIV	EQU	(APLL_DIV)
Startup_MPLL_DIV	EQU	(MPLL_DIV)

Startup_HCLKx2_DIV	EQU	(HCLKx2_DIV)

Startup_HCLK_DIV	EQU	(HCLK_DIV)
Startup_PCLK_DIV	EQU	(PCLK_DIV)
	[	CPU_NAME	= S3C6400
Startup_OND_DIV		EQU	(OND_DIV)
	]

Startup_ACLK		EQU	(((FIN>>APLL_SVAL)/APLL_PVAL)*APLL_MVAL)	; APLL Clock
Startup_MCLK		EQU	(((FIN>>MPLL_SVAL)/MPLL_PVAL)*MPLL_MVAL)	; MPLL Clock

	[ CPU_NAME = S3C6410
		[ SYNCMODE
; for Synchronous Mode
Startup_HCLK		EQU	(Startup_ACLK/(Startup_HCLKx2_DIV+1)/(Startup_HCLK_DIV+1))
		|		
; for Asynchronous Mode
Startup_HCLK		EQU	(Startup_MCLK/(Startup_HCLKx2_DIV+1)/(Startup_HCLK_DIV+1))
		]
	]
	[ CPU_NAME = S3C6400
; Only for Asynchronous Mode
Startup_HCLK		EQU	(Startup_MCLK/(Startup_HCLKx2_DIV+1)/(Startup_HCLK_DIV+1))
	]
;---------------------------
; CPSR Mode Bit Definition
;---------------------------
Mode_USR	EQU	(0x10)
Mode_FIQ	EQU	(0x11)
Mode_IRQ	EQU	(0x12)
Mode_SVC	EQU	(0x13)
Mode_ABT	EQU	(0x17)
Mode_UND	EQU	(0x1B)
Mode_SYS	EQU	(0x1F)
Mode_MASK	EQU	(0x1F)
NOINT		EQU	(0xC0)
I_Bit		EQU	(0x80)
F_Bit		EQU	(0x40)

;---------------------------
; CP15 Mode Bit Definition
;---------------------------
R1_iA		EQU	(1<<31)
R1_nF		EQU	(1<<30)
R1_VE		EQU	(1<<24)
R1_I		EQU	(1<<12)
R1_BP		EQU	(1<<11)	; Z bit
R1_C		EQU	(1<<2)
R1_A		EQU	(1<<1)
R1_M		EQU	(1<<0)

;---------------------------
;  Miscellaneous defines
;---------------------------
WORD_SIZE	EQU	(4)
DW8		EQU	(0x0)
DW16		EQU	(0x1)
DW32		EQU	(0x2)
WAIT		EQU	(0x1<<2)
UBLB		EQU	(0x1<<3)

;---------------------------
;
;  SFR Address
;
;---------------------------


;---------------------------
;  SysCon
;---------------------------

APLL_LOCK		EQU	(0x7e00f000)
MPLL_LOCK		EQU	(0x7e00f004)
APLL_CON		EQU	(0x7e00f00c)
MPLL_CON		EQU	(0x7e00f010)
EPLL_CON0		EQU	(0x7e00f014)
EPLL_CON1		EQU	(0x7e00f018)
CLK_SRC			EQU	(0x7e00f01c)
CLK_DIV0		EQU	(0x7e00f020)
CLK_OUT			EQU	(0x7e00f02c)
MEM_SYS_CFG		EQU	(0x7e00f120)
OTHERS			EQU	(0x7e00f900)
RST_STAT		EQU	(0x7E00F904)
INFORM0			EQU	(0x7E00FA00)
INFORM1			EQU	(0x7E00FA04)
INFORM2			EQU	(0x7E00FA08)
INFORM3			EQU	(0x7E00FA0C)

vPWR_CFG		EQU	(0xB2A0F804)
vSLEEP_CFG		EQU	(0xB2A0F818)
vOSC_STABLE		EQU	(0xB2A0F824)
vPWR_STABLE		EQU	(0xB2A0F828)
vRST_STAT		EQU	(0xB2A0F904)
vINFORM0		EQU	(0xB2A0FA00)
vINFORM1		EQU	(0xB2A0FA04)
vINFORM2		EQU	(0xB2A0FA08)
vINFORM3		EQU	(0xB2A0FA0C)

;---------------------------
;  GPIO
;---------------------------
GPACON		EQU	(S3C6410_BASE_REG_PA_GPIO + 0x000)
;GPHCON0	EQU	(S3C6410_BASE_REG_PA_IOPORT + 0x0E0)
;GPHCON1	EQU	(S3C6410_BASE_REG_PA_IOPORT + 0x0E4)
;GPHDAT		EQU	(S3C6410_BASE_REG_PA_IOPORT + 0x0E8)
;GPHPUD		EQU	(S3C6410_BASE_REG_PA_IOPORT + 0x0EC)

;GPH_OneND	EQU	0x2

GPNCON		EQU	(S3C6410_BASE_REG_PA_GPIO + 0x830)
GPNDAT		EQU	(S3C6410_BASE_REG_PA_GPIO + 0x834)
GPNPUD		EQU	(S3C6410_BASE_REG_PA_GPIO + 0x838)

	[ CPU_NAME = S3C6410
MEM1DRVCON	EQU	(S3C6410_BASE_REG_PA_GPIO + 0x1D4) 
MEM0DRVCON	EQU	(S3C6410_BASE_REG_PA_GPIO + 0x1D0) 
	]
;// 0x7F000000 -> 0x92B00000

;vGPHCON0	EQU	(0xB2B08000 + 0x0E0)
;vGPHCON1	EQU	(0xB2B08000 + 0x0E4)
;vGPHDAT	EQU	(0xB2B08000 + 0x0E8)
;vGPHPUD	EQU	(0xB2B08000 + 0x0EC)

vGPNCON					EQU	(0xB2B08000 + 0x830)
vGPNDAT					EQU	(0xB2B08000 + 0x834)
vGPNPUD					EQU	(0xB2B08000 + 0x838)

;vGPNCON		EQU	(0xB2B08830)
vEINT0CON0		EQU	(0xB2B08900)

;---------------------------
;  VIC
;---------------------------
VIC0INTENCLEAR		EQU	(S3C6410_BASE_REG_PA_VIC0 + 0x14)
VIC1INTENCLEAR		EQU	(S3C6410_BASE_REG_PA_VIC1 + 0x14)

vVIC0INTENABLE		EQU     (0xB0600010) ; VIC0
vVIC0INTENCLEAR		EQU     (0xB0600014) ; VIC0

vVIC1INTENABLE		EQU     (0xB0700010) ; VIC1
vVIC1INTENCLEAR		EQU     (0xB0700014) ; VIC1

NFDATA		EQU	0x70200010	; NAND Flash data register

;-----------------------------------
; Watch Dog Timer
;-----------------------------------
WTCON		EQU	(0x7e004000)

;=================
; SMC
;=================
SMBIDCYR0				EQU	0x70000000
SMBWSTRDR0				EQU	0x70000004
SMBWSTWRR0				EQU	0x70000008
SMBWSTOENR0				EQU	0x7000000c
SMBWSTWENR0				EQU	0x70000010
SMBCR0					EQU	0x70000014
SMBSR0					EQU	0x70000018
SMBWSTBRDR0				EQU	0x7000001c

SMBIDCYR1				EQU	0x70000020
SMBWSTRDR1				EQU	0x70000024
SMBWSTWRR1				EQU	0x70000028
SMBWSTOENR1				EQU	0x7000002c
SMBWSTWENR1				EQU	0x70000030
SMBCR1					EQU	0x70000034
SMBSR1					EQU	0x70000038
SMBWSTBRDR1				EQU	0x7000003c

SMBIDCYR2				EQU	0x70000040
SMBWSTRDR2				EQU	0x70000044
SMBWSTWRR2				EQU	0x70000048
SMBWSTOENR2				EQU	0x7000004c
SMBWSTWENR2				EQU	0x70000050
SMBCR2					EQU	0x70000054
SMBSR2					EQU	0x70000058
SMBWSTBRDR2				EQU	0x7000005c

SMBIDCYR3				EQU	0x70000060
SMBWSTRDR3				EQU	0x70000064
SMBWSTWRR3				EQU	0x70000068
SMBWSTOENR3				EQU	0x7000006c
SMBWSTWENR3				EQU	0x70000070
SMBCR3					EQU	0x70000074
SMBSR3					EQU	0x70000078
SMBWSTBRDR3				EQU	0x7000007c

SMBIDCYR4				EQU	0x70000080
SMBWSTRDR4				EQU	0x70000084
SMBWSTWRR4				EQU	0x70000088
SMBWSTOENR4				EQU	0x7000008c
SMBWSTWENR4				EQU	0x70000090
SMBCR4					EQU	0x70000094
SMBSR4					EQU	0x70000098
SMBWSTBRDR4				EQU	0x7000009c

SMBIDCYR5				EQU	0x700000a0
SMBWSTRDR5				EQU	0x700000a4
SMBWSTWRR5				EQU	0x700000a8
SMBWSTOENR5				EQU	0x700000ac
SMBWSTWENR5				EQU	0x700000b0
SMBCR5					EQU	0x700000b4
SMBSR5					EQU	0x700000b8
SMBWSTBRDR5				EQU	0x700000bc

SMBIDCYR6				EQU	0x700000c0
SMBWSTRDR6				EQU	0x700000c4
SMBWSTWRR6				EQU	0x700000c8
SMBWSTOENR6				EQU	0x700000cc
SMBWSTWENR6				EQU	0x700000d0
SMBCR6					EQU	0x700000d4
SMBSR6					EQU	0x700000d8
SMBWSTBRDR6				EQU	0x700000dc

SMBIDCYR7				EQU	0x700000e0
SMBWSTRDR7				EQU	0x700000e4
SMBWSTWRR7				EQU	0x700000e8
SMBWSTOENR7				EQU	0x700000ec
SMBWSTWENR7				EQU	0x700000f0
SMBCR7					EQU	0x700000f4
SMBSR7					EQU	0x700000f8
SMBWSTBRDR7				EQU	0x700000fc



;=================
; DMC
;=================
DMC0_BASE			EQU	0x7e000000
DMC1_BASE			EQU	0x7e001000

INDEX_MEMSTAT			EQU	0x0
INDEX_MEMCCMD			EQU	0x4
INDEX_DIRECTCMD			EQU	0x8
INDEX_MEMCFG			EQU	0xc
INDEX_REFRESH			EQU	0x10
INDEX_CASLAT			EQU	0x14
INDEX_T_DQSS			EQU	0x18
INDEX_T_MRD			EQU	0x1c
INDEX_T_RAS			EQU	0x20
INDEX_T_RC			EQU	0x24
INDEX_T_RCD			EQU	0x28
INDEX_T_RFC			EQU	0x2c
INDEX_T_RP			EQU	0x30
INDEX_T_RRD			EQU	0x34
INDEX_T_WR			EQU	0x38
INDEX_T_WTR			EQU	0x3c
INDEX_T_XP			EQU	0x40
INDEX_T_XSR			EQU	0x44
INDEX_T_ESR			EQU	0x48
INDEX_MEMCFG2			EQU	0x4c
INDEX_ID_0_CFG			EQU	0x100
INDEX_ID_1_CFG			EQU	0x104
INDEX_ID_2_CFG			EQU	0x108
INDEX_ID_3_CFG			EQU	0x10c
INDEX_ID_4_CFG			EQU	0x110
INDEX_ID_5_CFG			EQU	0x114
INDEX_ID_6_CFG			EQU	0x118
INDEX_ID_7_CFG			EQU	0x11c
INDEX_ID_8_CFG			EQU	0x120
INDEX_ID_9_CFG			EQU	0x124
INDEX_ID_10_CFG			EQU	0x128
INDEX_ID_11_CFG			EQU	0x12c
INDEX_ID_12_CFG			EQU	0x130
INDEX_ID_13_CFG			EQU	0x134
INDEX_ID_14_CFG			EQU	0x138
INDEX_ID_15_CFG			EQU	0x13c
INDEX_CHIP0_CFG			EQU	0x200
INDEX_CHIP1_CFG			EQU	0x204
INDEX_USER_STAT			EQU	0x300
INDEX_USER_CFG			EQU	0x304

;-------------------------------------------------------------------------------
; Memory Chip direct command
;-------------------------------------------------------------------------------
DMC_NOP0		EQU	0x0c0000
DMC_NOP1		EQU 	0x1c0000
DMC_PA0			EQU	0x000000	; Precharge all
DMC_PA1			EQU 	0x100000
DMC_AR0			EQU 	0x040000	; Autorefresh
DMC_AR1			EQU 	0x140000
DMC_SDR_MR0		EQU	0x080032	; MRS, CAS 3, Burst Length 4
DMC_SDR_MR1		EQU	0x180032
DMC_DDR_MR0		EQU 	0x080162
DMC_DDR_MR1		EQU 	0x180162
DMC_mDDR_MR0		EQU	0x080032	; CAS 3, Burst Length 4
DMC_mDDR_MR1		EQU 	0x180032
DMC_mSDR_EMR0		EQU 	0x0a0000	; EMRS, DS:Full, PASR:Full Array
DMC_mSDR_EMR1		EQU 	0x1a0000
DMC_DDR_EMR0		EQU 	0x090000
DMC_DDR_EMR1		EQU 	0x190000
DMC_mDDR_EMR0		EQU 	0x0a0000	; DS:Full, PASR:Full Array
DMC_mDDR_EMR1		EQU 	0x1a0000

	END