s3c6410.inc

来自「SAMSUNG S3C6410 CPU BSP for winmobile6」· INC 代码 · 共 717 行 · 第 1/2 页

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;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;-------------------------------------------------------------------------------
;
;  Header: s3c6410.inc
;
;  This header file defines only those registers required by the startup
;  code. All addresses are based off the physical addresses (PA) defined
;  in s3c6410_base_reg.h (s3c6410_base_reg.inc).
;
;-------------------------------------------------------------------------------

; Include the base register definitions
;-------------------------------------------------------------------------------
; Definitions for POP Option
; POP_OPTION : 0, S3C6410
; POP_OPTION : 1, SC36410-X5A  --> S3C6410 + OneNAND(256MB) + mDDR(128MB)
;-------------------------------------------------------------------------------
POP_NONE	EQU	0
POP_X5A		EQU	1


	GBLA	POP_OPTION

;-------------------------------------------------
; Change Package Option for Package Types
;-------------------------------------------------
;POP_OPTION	SETA	POP_X5A
POP_OPTION	SETA	POP_NONE
;-------------------------------------------------




;------------------------------------------------------------------------------
; CPU_Name Definition 
;------------------------------------------------------------------------------
S3C6400		EQU	1
S3C6410		EQU	2

	;INCLUDE s3c6410_base_regs.inc

;-------------------------------------------------
; CPU Revision Definition
;-------------------------------------------------
EVT1		EQU	1
EVT2		EQU	2

;-------------------------------------------------
; System Clock Definition
;-------------------------------------------------

CLK_200MHZ	EQU	200000000
CLK_266MHZ	EQU	266000000
CLK_300MHZ	EQU	300000000
CLK_400MHZ	EQU	400000000
CLK_532MHZ	EQU	532000000
CLK_634MHZ	EQU	634000000

ECLK_96MHZ	EQU	96000000
ECLK_84MHZ	EQU	84666667	; for IIS 44.1 KHz
ECLK_92MHZ	EQU	92160000	; for IIS 48 KHz

	GBLA	CPU_NAME
	GBLA	CPU_REVISION
	GBLA	S3C6410_APLL_CLK
	GBLA	S3C6410_ECLK
	GBLL	CHANGE_PLL_CLKDIV_ON_EBOOT
	GBLL	CHANGE_PLL_CLKDIV_ON_KERNEL
	GBLL	CLEAR_DRAM_ON_EBOOT
	GBLL	CLEAR_DRAM_ON_KERNEL

CHANGE_PLL_CLKDIV_ON_EBOOT	SETL	{TRUE}
CHANGE_PLL_CLKDIV_ON_KERNEL	SETL	{FALSE}
CLEAR_DRAM_ON_EBOOT		SETL	{FALSE}
CLEAR_DRAM_ON_KERNEL		SETL	{FALSE}
	

;------------------------------------------------------------------------------
; Define: CPU_Name 
;
; CPU_Name used to make bsp compatible between previous platform and new released platform
;------------------------------------------------------------------------------
CPU_NAME	SETA	S3C6410

;------------------------------------------------------------------------------
; Define: SYNCMODE 
;
; SYNCMODE used to set cpu operation mode to syncronous mode or asyncronous mode
;------------------------------------------------------------------------------

	[ CPU_NAME = S3C6410
	GBLL	SYNCMODE
	
SYNCMODE	SETL	{TRUE}
CLK_667MHZ	EQU	667000000
CLK_800MHZ	EQU	800000000				; Just for the test, remove when release
CLK_1066MHZ	EQU	1066000000			; Just for the test, remove when release
	]

;-------------------------------------------------
; Change CPU Revision (EVT0 is no longer supported)
;-------------------------------------------------
;CPU_REVISION	SETA	EVT1
CPU_REVISION	SETA	EVT2
;-------------------------------------------------

;-------------------------------------------------
; Change S3C6410_APLL_CLK definition for StartUp code
;-------------------------------------------------
;S3C6410_APLL_CLK	SETA	CLK_400MHZ
S3C6410_APLL_CLK	SETA	CLK_532MHZ
;S3C6410_APLL_CLK	SETA	CLK_634MHZ
	[ CPU_NAME = S3C6410			; This configuration will work only on S3C6410
;S3C6410_APLL_CLK	SETA	CLK_667MHZ
;S3C6410_APLL_CLK	SETA	CLK_800MHZ
;S3C6410_APLL_CLK	SETA	CLK_1066MHZ
	]
FIN		EQU	12000000
;-------------------------------------------------

; Include the base register definitions

	INCLUDE s3c6410_base_regs.inc


;-------------------------------------------------
; Note!!! : EVT1 support Only 400 MHz
;-------------------------------------------------
	[ CPU_REVISION = EVT1
S3C6410_APLL_CLK	SETA	CLK_400MHZ
	]
;-------------------------------------------------

;-------------------------------------------------
; Change S3C6410_ECLK definition for EPLL Fout
;-------------------------------------------------
;S3C6410_ECLK	SETA	ECLK_96MHZ
S3C6410_ECLK	SETA	ECLK_84MHZ
;S3C6410_ECLK	SETA	ECLK_92MHZ
;-------------------------------------------------


	; 400:100:25 (S3C6410 support only Asyncronous Mode)
	[ S3C6410_APLL_CLK = CLK_400MHZ

		[ CPU_REVISION = EVT1

;Fvco=1600MHz, Fout=400MHz
APLL_MVAL	EQU	(400)
APLL_PVAL	EQU	(3)
APLL_SVAL	EQU	(2)

;Fvco=1600MHz, Fout=200MHz
MPLL_MVAL	EQU	(400)
MPLL_PVAL	EQU	(3)
MPLL_SVAL	EQU	(3)

		|

;Fvco=800MHz, Fout=400MHz
APLL_MVAL	EQU	(400)
APLL_PVAL	EQU	(6)
APLL_SVAL	EQU	(1)

;Fvco=800MHz, Fout=200MHz
MPLL_MVAL	EQU	(400)
MPLL_PVAL	EQU	(6)
MPLL_SVAL	EQU	(2)

		]

APLL_DIV	EQU	(1-1)	; ARMCLK = 400 MHz
MPLL_DIV	EQU	(2-1)	; DOUT_MPLL = MPLL_Fout/2 (100 MHz)

HCLKx2_DIV	EQU	(1-1)	; HCLKx2 = MPLL_Fout	(200 MHz)

HCLK_DIV	EQU	(2-1)	; AHB_CLK = HCLKx2/2	(100 MHz)
PCLK_DIV	EQU	(8-1)	; PCLK = HCLKx2/8	(25 MHz)
	[ POP_OPTION = POP_NONE
OND_DIV		EQU	(4-1)	; OND_CLK = HCLKx2/4	(50 MHz)
	]
	[ POP_OPTION = POP_X5A
OND_DIV		EQU	(1-1)	; OND_CLK = HCLK	(50 MHz)
	]

S3C6410_ACLK	EQU	(S3C6410_APLL_CLK/(APLL_DIV+1))	; ARMCLK = 400 MHz
  	]	; 400 MHz

	; 532:133:33 (S3C6410 support only Asyncronous Mode)
	[ S3C6410_APLL_CLK = CLK_532MHZ
		[ CPU_NAME = S3C6410
;Fvco=1064MHz, Fout=532MHz
APLL_MVAL	EQU	(266)
APLL_PVAL	EQU	(3)
APLL_SVAL	EQU	(1)

;Fvco=1064MHz, Fout=266MHz
MPLL_MVAL	EQU	(266)
MPLL_PVAL	EQU	(3)
MPLL_SVAL	EQU	(2)

APLL_DIV	EQU	(1-1)	; ARMCLK = 532 MHz
MPLL_DIV	EQU	(2-1)	; DOUT_MPLL = MPLL_Fout/2 (133 MHz)
			[ SYNCMODE
HCLKx2_DIV	EQU	(2-1)	; HCLKx2 = APLL_Fout/2	(266 MHz)
			|
HCLKx2_DIV	EQU	(1-1)	; HCLKx2 = MPLL_Fout	(266 MHz)
			]

HCLK_DIV	EQU	(2-1)	; AHB_CLK = HCLKx2/2	(133 MHz)
PCLK_DIV	EQU	(8-1)	; PCLK = HCLKx2/8	(33.25 MHz)
OND_DIV		EQU	(4-1)	; OND_CLK = HCLKx2/4	(66.5 MHz)

S3C6410_ACLK	EQU	(S3C6410_APLL_CLK/(APLL_DIV+1))	; ARMCLK = 532 MHz
		]
		[ CPU_NAME = S3C6400
;Fvco=1064MHz, Fout=532MHz
APLL_MVAL	EQU	(532)
APLL_PVAL	EQU	(6)
APLL_SVAL	EQU	(1)

;Fvco=1064MHz, Fout=266MHz
MPLL_MVAL	EQU	(532)
MPLL_PVAL	EQU	(6)
MPLL_SVAL	EQU	(2)

APLL_DIV	EQU	(1-1)	; ARMCLK = 532 MHz
MPLL_DIV	EQU	(2-1)	; DOUT_MPLL = MPLL_Fout/2 (133 MHz)

HCLKx2_DIV	EQU	(1-1)	; HCLKx2 = MPLL_Fout	(266 MHz)

HCLK_DIV	EQU	(2-1)	; AHB_CLK = HCLKx2/2	(133 MHz)
PCLK_DIV	EQU	(8-1)	; PCLK = HCLKx2/8	(33.25 MHz)
	[ POP_OPTION = POP_NONE
OND_DIV		EQU	(4-1)	; OND_CLK = HCLKx2/4	(66.5 MHz)
	]
	[ POP_OPTION = POP_X5A
OND_DIV		EQU	(1-1)	; OND_CLK = HCLK	(66.5 MHz)
	]

S3C6410_ACLK	EQU	(S3C6410_APLL_CLK/(APLL_DIV+1))	; ARMCLK = 532 MHz
		]
  	]	; 532 MHz

	; 634:133:66.5 (S3C6410 support only Asyncronous Mode)
	[ S3C6410_APLL_CLK = CLK_634MHZ

;Fvco=1268MHz, Fout=634MHz
APLL_MVAL	EQU	(634)
APLL_PVAL	EQU	(6)
APLL_SVAL	EQU	(1)

;Fvco=1064MHz, Fout=266MHz
MPLL_MVAL	EQU	(532)
MPLL_PVAL	EQU	(6)
MPLL_SVAL	EQU	(2)

APLL_DIV	EQU	(1-1)	; ARMCLK = 634 MHz
MPLL_DIV	EQU	(2-1)	; DOUT_MPLL = MPLL_Fout/2 (133 MHz)

HCLKx2_DIV	EQU	(1-1)	; HCLKx2 = MPLL_Fout	(266 MHz)

HCLK_DIV	EQU	(2-1)	; AHB_CLK = HCLKx2/2	(133 MHz)
PCLK_DIV	EQU	(8-1)	; PCLK = HCLKx2/8	(33.25 MHz)
	[ POP_OPTION = POP_NONE
OND_DIV		EQU	(4-1)	; OND_CLK = HCLKx2/4	(66.5 MHz)
	]
	[ POP_OPTION = POP_X5A
OND_DIV		EQU	(1-1)	; OND_CLK = HCLK	(66.5 MHz)
	]

S3C6410_ACLK	EQU	(S3C6410_APLL_CLK/(APLL_DIV+1))	; ARMCLK = 634 MHz

	]	; 634 MHz

	[ CPU_NAME = S3C6410
	; 667:133:33 (S3C6410 support only Asyncronous Mode)
		[ S3C6410_APLL_CLK = CLK_667MHZ

;Fvco=1268MHz, Fout=667MHz
APLL_MVAL	EQU	(667)
APLL_PVAL	EQU	(6)
APLL_SVAL	EQU	(1)

;Fvco=1064MHz, Fout=266MHz
MPLL_MVAL	EQU	(266)
MPLL_PVAL	EQU	(3)
MPLL_SVAL	EQU	(2)

APLL_DIV	EQU	(1-1)	; ARMCLK = 667 MHz
MPLL_DIV	EQU	(2-1)	; DOUT_MPLL = MPLL_Fout/2 (133 MHz)

HCLKx2_DIV	EQU	(1-1)	; HCLKx2 = MPLL_Fout	(266 MHz)

HCLK_DIV	EQU	(2-1)	; AHB_CLK = HCLKx2/2	(133 MHz)
PCLK_DIV	EQU	(8-1)	; PCLK = HCLKx2/8	(33.25 MHz)
OND_DIV		EQU	(4-1)	; OND_CLK = HCLKx2/4	(66.5 MHz)

S3C6410_ACLK	EQU	(S3C6410_APLL_CLK/(APLL_DIV+1))	; ARMCLK = 667 MHz

		]	; 667 MHz

	; 800:133:33 (S3C6410 support only Syncronous Mode)
		[ S3C6410_APLL_CLK = CLK_800MHZ

;Fvco=1600MHz, Fout=800MHz
APLL_MVAL	EQU	(400)
APLL_PVAL	EQU	(3)
APLL_SVAL	EQU	(1)

;Fvco=1600MHz, Fout=266MHz
MPLL_MVAL	EQU	(266)	; 400
MPLL_PVAL	EQU	(3)	; 18
MPLL_SVAL	EQU	(2)		; 0

APLL_DIV	EQU	(1-1)	; ARMCLK = 800 MHz
MPLL_DIV	EQU	(2-1)	; DOUT_MPLL = MPLL_Fout/2 (133 MHz)

HCLKx2_DIV	EQU	(3-1)	; HCLKx2 = APLL_Fout/3	(266 MHz)

HCLK_DIV	EQU	(2-1)	; AHB_CLK = HCLKx2/2	(133 MHz)
PCLK_DIV	EQU	(8-1)	; PCLK = HCLKx2/8	(33.25 MHz)


S3C6410_ACLK	EQU	(S3C6410_APLL_CLK/(APLL_DIV+1))	; ARMCLK = 800 MHz

		]	; 800 MHz		

	; 1066:133:33 (S3C6410 support only Syncronous Mode)
		[ S3C6410_APLL_CLK = CLK_1066MHZ

;Fvco=1600MHz, Fout=1066MHz
APLL_MVAL	EQU	(533)
APLL_PVAL	EQU	(3)
APLL_SVAL	EQU	(1)

;Fvco=1600MHz, Fout=266MHz
MPLL_MVAL	EQU	(266)	; 400
MPLL_PVAL	EQU	(3)	; 18
MPLL_SVAL	EQU	(2)		; 0

APLL_DIV	EQU	(1-1)	; ARMCLK = 1066 MHz
MPLL_DIV	EQU	(2-1)	; DOUT_MPLL = MPLL_Fout/2 (133 MHz)

HCLKx2_DIV	EQU	(4-1)	; HCLKx2 = APLL_Fout/4	(266 MHz)

HCLK_DIV	EQU	(2-1)	; AHB_CLK = HCLKx2/2	(133 MHz)
PCLK_DIV	EQU	(8-1)	; PCLK = HCLKx2/8	(33.25 MHz)
12

s3c6410.inc - 源码说明

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