bsp_cfg.h

SAMSUNG S3C6410 CPU BSP for winmobile6

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  File:  bsp_cfg.h
//
//  This file contains system constant specific for SMDK6410 board.
//
#ifndef __BSP_CFG_H
#define __BSP_CFG_H

//------------------------------------------------------------------------------
//
//  Define:  BSP_DEVICE_PREFIX
//
//  Prefix used to generate device name for bootload/KITL
//
#define BSP_DEVICE_PREFIX       "SMDK6410"        // Device name prefix

//------------------------------------------------------------------------------
// Define: CPU_Name 
//
// CPU_Name used to make bsp compatible between previous platform and new released platform
//------------------------------------------------------------------------------
#define S3C6400		(1)
#define S3C6410		(2)
#define CPU_NAME	(S3C6410)

#if	(CPU_NAME == S3C6410)
//------------------------------------------------------------------------------
// Define: SYNCMODE 
//
// SYNCMODE used to set cpu operation mode to syncronous mode or asyncronous mode
//------------------------------------------------------------------------------
#define SYNCMODE		(TRUE)
#endif

//------------------------------------------------------------------------------
// CPU Revision (EVT0 is no longer supported)
//------------------------------------------------------------------------------
#define EVT1		(1)
#define EVT2		(2)
#define CPU_REVISION	(EVT2)

//------------------------------------------------------------------------------
// System Clock Definition
//------------------------------------------------------------------------------
#define CLK_25MHz		25000000
#define CLK_50MHz		50000000
#define CLK_33_25MHz	33250000
#define CLK_66_5MHz		66500000
#define CLK_96MHz		96000000
#define CLK_100MHz		100000000
#define CLK_133MHz		133000000
#define CLK_200MHz		200000000
#define CLK_233MHz		233000000
#define CLK_266MHz		266000000
#define CLK_300MHz		300000000
#define CLK_400MHz		400000000
#define CLK_532MHz		532000000
#define CLK_634MHz		634000000
#if 	(CPU_NAME == S3C6410)
#define CLK_667MHz		667000000
#define CLK_800MHz		800000000			// Just for the Test, Remove when release
#define CLK_1066MHz		1066000000		// Just for the Test, Remove when release
#endif
// FCLK->CLK.. mod by shin.0313

// Change This Definition to choose BSP Clock !!! (and "s3c6410.inc")
//#define S3C6410_APLL_CLK	FCLK_400MHz
#define S3C6410_APLL_CLK	CLK_532MHz
//#define S3C6410_APLL_CLK	CLK_634MHz

#if	(CPU_NAME == S3C6410)		// This configuration will work only on S3C6410
//#define S3C6410_APLL_CLK	CLK_667MHz
//#define	S3C6410_APLL_CLK	CLK_800MHz
//#define	S3C6410_APLL_CLK	CLK_1066MHz
#endif


#if	(CPU_REVISION == EVT1)	// EVT1 support Only 400 MHz
#undef S3C6410_APLL_CLK
#define S3C6410_APLL_CLK	CLK_400MHz
#endif

#if		(S3C6410_APLL_CLK == CLK_400MHz)			// ARM:HCLK:PCLK = 400:100:25 (Sync Mode)

#define APLL_CLK				(S3C6410_APLL_CLK)
#define MPLL_CLK				(CLK_200MHz)

#define APLL_DIV				1
#define MPLL_DIV				2
#define HCLKx2_DIV			1	// Async
#define HCLK_DIV				2
#define PCLK_DIV				8

#define S3C6410_ACLK		(APLL_CLK/APLL_DIV)			// 400 MHz
#define S3C6410_DoutMPLL 	(MPLL_CLK/MPLL_DIV)			// 100 MHz
#define S3C6410_HCLKx2		(MPLL_CLK/HCLKx2_DIV)		// 200 MHz
#define S3C6410_HCLK		(S3C6410_HCLKx2/HCLK_DIV)	// 100 MHz
#define S3C6410_PCLK		(S3C6410_HCLKx2/PCLK_DIV)	// 25 MHz

#elif	(S3C6410_APLL_CLK == CLK_532MHz)			// ARM:HCLK:PCLK = 532:133:33.25 (Sync Mode)

#define APLL_CLK				(S3C6410_APLL_CLK)
#define MPLL_CLK				(CLK_266MHz)

#define APLL_DIV				1
#define MPLL_DIV				2
#if		(CPU_NAME == S3C6410)
#if		(SYNCMODE)
#define HCLKx2_DIV			2	// Async
#else
#define HCLKx2_DIV			1	// Async
#endif
#elif	(CPU_NAME == S3C6400)
#define HCLKx2_DIV			1	// Async
#endif
#define HCLK_DIV				2
#define PCLK_DIV				8

#define S3C6410_ACLK		(APLL_CLK/APLL_DIV)			// 532 MHz
#define S3C6410_DoutMPLL 	(MPLL_CLK/MPLL_DIV)			// 133 MHz
#if		(CPU_NAME == S3C6410)
#if		(SYNCMODE)
#define S3C6410_HCLKx2		(APLL_CLK/HCLKx2_DIV)		// 266 MHz
#else
#define S3C6410_HCLKx2		(MPLL_CLK/HCLKx2_DIV)		// 266 MHz
#endif
#elif	(CPU_NAME == S3C6400)
#define S3C6410_HCLKx2		(MPLL_CLK/HCLKx2_DIV)		// 266 MHz
#endif
#define S3C6410_HCLK		(S3C6410_HCLKx2/HCLK_DIV)	// 133 MHz
#define S3C6410_PCLK		(S3C6410_HCLKx2/PCLK_DIV)	// 33.25 MHz

#elif	(S3C6410_APLL_CLK == CLK_634MHz)			// ARM:HCLK:PCLK = 634:133:66.5 (Async Mode)

#define APLL_CLK				(S3C6410_APLL_CLK)
#define MPLL_CLK				(CLK_266MHz)

#define APLL_DIV				1
#define MPLL_DIV				2
#define HCLKx2_DIV			1	// Async
#define HCLK_DIV				2
#define PCLK_DIV				8

#define S3C6410_ACLK		(APLL_CLK/APLL_DIV)			// 634 MHz
#define S3C6410_DoutMPLL 	(MPLL_CLK/MPLL_DIV)			// 133 MHz
#define S3C6410_HCLKx2		(MPLL_CLK/HCLKx2_DIV)		// 266 MHz
#define S3C6410_HCLK		(S3C6410_HCLKx2/HCLK_DIV)	// 133 MHz
#define S3C6410_PCLK		(S3C6410_HCLKx2/PCLK_DIV)	// 33.25 MHz


#elif	(S3C6410_APLL_CLK == CLK_667MHz)			// ARM:HCLK:PCLK = 667:133:33.25 (Async Mode)
#if		(CPU_NAME == S3C6410)
#define APLL_CLK				(S3C6410_APLL_CLK)
#define MPLL_CLK				(CLK_266MHz)

#define APLL_DIV				1
#define MPLL_DIV				2
#define HCLKx2_DIV			1	// Async
#define HCLK_DIV				2
#define PCLK_DIV				8

#define S3C6410_ACLK		(APLL_CLK/APLL_DIV)			// 667 MHz
#define S3C6410_DoutMPLL 	(MPLL_CLK/MPLL_DIV)			// 133 MHz
#define S3C6410_HCLKx2		(MPLL_CLK/HCLKx2_DIV)		// 266 MHz
#define S3C6410_HCLK		(S3C6410_HCLKx2/HCLK_DIV)	// 133 MHz
#define S3C6410_PCLK		(S3C6410_HCLKx2/PCLK_DIV)	// 33.25 MHz
#elif	(CPU_NAME == S3C6400)
#error BSP_CLOCK_UNDEFINED_ERROR
#endif	// add by shin.0322

#elif	(S3C6410_APLL_CLK == CLK_800MHz)			// ARM:HCLK:PCLK = 800:133:33.25 (Sync Mode)
#if		(CPU_NAME == S3C6410)
#define APLL_CLK				(S3C6410_APLL_CLK)
#define MPLL_CLK				(CLK_266MHz)

#define APLL_DIV				1
#define MPLL_DIV				2
#define HCLKx2_DIV			3	// Sync
#define HCLK_DIV				2
#define PCLK_DIV				8

#define S3C6410_ACLK		(APLL_CLK/APLL_DIV)			// 800 MHz
#define S3C6410_DoutMPLL 	(MPLL_CLK/MPLL_DIV)			// 133 MHz
#define S3C6410_HCLKx2		(APLL_CLK/HCLKx2_DIV)		// 266 MHz
#define S3C6410_HCLK		(S3C6410_HCLKx2/HCLK_DIV)	// 133 MHz
#define S3C6410_PCLK		(S3C6410_HCLKx2/PCLK_DIV)	// 33.25 MHz
#elif	(CPU_NAME == S3C6400)
#error BSP_CLOCK_UNDEFINED_ERROR
#endif

#elif	(S3C6410_APLL_CLK == CLK_1066MHz)			// ARM:HCLK:PCLK = 800:133:33.25 (Sync Mode)
#if		(CPU_NAME == S3C6410)
#define APLL_CLK				(S3C6410_APLL_CLK)
#define MPLL_CLK				(CLK_266MHz)

#define APLL_DIV				1
#define MPLL_DIV				2
#define HCLKx2_DIV			4	// Sync
#define HCLK_DIV				2
#define PCLK_DIV				8

#define S3C6410_ACLK		(APLL_CLK/APLL_DIV)			// 1066 MHz
#define S3C6410_DoutMPLL 	(MPLL_CLK/MPLL_DIV)			// 133 MHz
#define S3C6410_HCLKx2		(APLL_CLK/HCLKx2_DIV)		// 266 MHz
#define S3C6410_HCLK		(S3C6410_HCLKx2/HCLK_DIV)	// 133 MHz
#define S3C6410_PCLK		(S3C6410_HCLKx2/PCLK_DIV)	// 33.25 MHz
#elif	(CPU_NAME == S3C6400)
#error BSP_CLOCK_UNDEFINED_ERROR
#endif
#else
#error BSP_CLOCK_UNDEFINED_ERROR
#endif

//------------------------------------------------------------------------------
// SMDK6410 EPLL Output Frequency
//------------------------------------------------------------------------------
//#define S3C6410_ECLK	(FCLK_96MHz)		// 96 MHz 		for USB Host, SD/HSMMC..
#define S3C6410_ECLK	(84666667)		// 84,666,667 Hz 	for IIS Sampling Rate 44.1 KHz (384fs)
//#define S3C6410_ECLK	(92160000)		// 92,160,000 Hz 	for IIS Sampling Rate 48 KHz (384fs)

//------------------------------------------------------------------------------
// System Tick Timer Definition
//------------------------------------------------------------------------------
// For Precision of System timer
// Use timer counter as large as possible. (32-bit Counter)
// Use timer divider as small as possible.
#define SYS_TIMER_PRESCALER	(2)	// PCLK / 2 (Do not use Prescaler as 1)
#define SYS_TIMER_DIVIDER		(1)
#define TICK_PER_SEC			(1000)
#define OEM_COUNT_1MS			(S3C6410_PCLK/SYS_TIMER_PRESCALER/SYS_TIMER_DIVIDER/TICK_PER_SEC-1)
#define RESCHED_PERIOD			(1)

#define PWM0_1_PRESCALER		((int)(S3C6410_PCLK/1000000)-1)
#define PWM1_DIVIDER			1   //PWM1 for backlight(1Count:2us)
//------------------------------------------------------------------------------
// SMDK6410 Display Dimension
//------------------------------------------------------------------------------
#define LCD_MODULE_LTS222		(0)	// Portrait 2.2" QVGA RGB16
#define LCD_MODULE_LTV350		(1)	// Landscape 3.5" QVGA RGB16
#define LCD_MODULE_LTE480		(2)	// Landscape 4.8" WVGA RGB16
#define LCD_MODULE_EMUL48_D1	(3)	// Landscape 4.8" WVGA RGB16 as D1 (720x480)
#define LCD_MODULE_EMUL48_QV	(4)	// Landscape 4.8" WVGA RGB16 as QVGA (320x240)
#define LCD_MODULE_EMUL48_PQV	(5)	// Landscape 4.8" WVGA RGB16 as PQVGA (240x320)
#define LCD_MODULE_EMUL48_ML	(6)	// Landscape 4.8" WVGA RGB16 as 480x320
#define LCD_MODULE_EMUL48_MP	(7)	// Landscape 4.8" WVGA RGB16 as 320x480
#define LCD_MODULE_LTP700		(8)	// Landscape 7" WVGA RGB24

#define LCD_TYPE_PORTRAIT		(0)
#define LCD_TYPE_LANDSCAPE		(1)

#define SMDK6410_LCD_MODULE	(LCD_MODULE_LTE480)

#if (SMDK6410_LCD_MODULE == LCD_MODULE_LTS222)
#define LCD_WIDTH			240
#define LCD_HEIGHT			320
#define LCD_BPP				16
#define LCD_TYPE			LCD_TYPE_PORTRAIT
#elif (SMDK6410_LCD_MODULE == LCD_MODULE_LTV350)
#define LCD_WIDTH			320
#define LCD_HEIGHT			240
#define LCD_BPP				16
#define LCD_TYPE			LCD_TYPE_LANDSCAPE
#elif (SMDK6410_LCD_MODULE == LCD_MODULE_LTE480)
#define LCD_WIDTH			800
#define LCD_HEIGHT			480
#define LCD_BPP				16
#define LCD_TYPE			LCD_TYPE_LANDSCAPE
#elif (SMDK6410_LCD_MODULE == LCD_MODULE_EMUL48_D1)
#define LCD_WIDTH			720
#define LCD_HEIGHT			480
#define LCD_BPP				16
#define LCD_TYPE			LCD_TYPE_LANDSCAPE
#elif (SMDK6410_LCD_MODULE == LCD_MODULE_EMUL48_QV)
#define LCD_WIDTH			320
#define LCD_HEIGHT			240
#define LCD_BPP				16
#define LCD_TYPE			LCD_TYPE_LANDSCAPE
#elif (SMDK6410_LCD_MODULE == LCD_MODULE_EMUL48_PQV)
#define LCD_WIDTH			240
#define LCD_HEIGHT			320
#define LCD_BPP				16
#define LCD_TYPE			LCD_TYPE_PORTRAIT
#elif (SMDK6410_LCD_MODULE == LCD_MODULE_EMUL48_ML)
#define LCD_WIDTH			480
#define LCD_HEIGHT			320
#define LCD_BPP				16
#define LCD_TYPE			LCD_TYPE_LANDSCAPE
#elif (SMDK6410_LCD_MODULE == LCD_MODULE_EMUL48_MP)
#define LCD_WIDTH			320
#define LCD_HEIGHT			480
#define LCD_BPP				16
#define LCD_TYPE			LCD_TYPE_PORTRAIT
#elif (SMDK6410_LCD_MODULE == LCD_MODULE_LTP700)
#define LCD_WIDTH			800
#define LCD_HEIGHT			480
#define LCD_BPP				32	// rgb888 XRGB
#define LCD_TYPE			LCD_TYPE_LANDSCAPE
#else
#error LCD_MODULE_UNDEFINED_ERROR
#endif

//------------------------------------------------------------------------------
// SMDK6410 Audio Sampling Rate
//------------------------------------------------------------------------------
#define AUDIO_44_1KHz		(44100)
#define AUDIO_48KHz			(48000)
#define AUDIO_SAMPLE_RATE	(AUDIO_44_1KHz)		// Keep sync with EPLL Fout

//------------------------------------------------------------------------------
// SMDK6410 UART Debug Port Baudrate
//------------------------------------------------------------------------------
#define DEBUG_UART0		(0)
#define DEBUG_UART1		(1)
#define DEBUG_UART2		(2)
#define DEBUG_UART3		(3)
#define DEBUG_BAUDRATE		(115200)

//------------------------------------------------------------------------------
// SMDK6410 NAND Flash Timing Parameter
//------------------------------------------------------------------------------
#if	(S3C6410_HCLK == CLK_100MHz)
#define NAND_TACLS			(7)
#define NAND_TWRPH0		(7)
#define NAND_TWRPH1		(7)
#elif	(S3C6410_HCLK == CLK_133MHz)
#define NAND_TACLS			(7)
#define NAND_TWRPH0		(7)
#define NAND_TWRPH1		(7)
#elif	(S3C6410_HCLK == CLK_1333MHz)
#define NAND_TACLS			(7)
#define NAND_TWRPH0		(7)
#define NAND_TWRPH1		(7)
#else
#error NAND_TIMING_UNDEFINED_ERROR
#endif

//------------------------------------------------------------------------------
// SMDK6410 CF Interface Mode
//------------------------------------------------------------------------------
#define CF_INDIRECT_MODE	(0)		// MemPort0 Shared by EBI
#define CF_DIRECT_MODE		(1)		// Independent CF Interface
#define CF_INTERFACE_MODE	(CF_DIRECT_MODE)

//------------------------------------------------------------------------------
// SMDK6410 Static SYSINTR Definition
//------------------------------------------------------------------------------
#define SYSINTR_OHCI 		(SYSINTR_FIRMWARE+1)	// for USB Host

//------------------------------------------------------------------------------
// SMDK6410 BSP Debug Option
//------------------------------------------------------------------------------
#define REMOVE_BEFORE_RELEASE		// Define this will remove debug message or somthing...

//------------------------------------------------------------------------------
// SMDK6410 Keypad Layout
//------------------------------------------------------------------------------
#if		(CPU_NAME == S3C6410)
#define LAYOUT0				(0)		// 8*8 Keyppad board
#define LAYOUT1				(1)		// On-Board Key
#define LAYOUT2				(2)		// Qwerty Key board
#define MATRIX_LAYOUT		(LAYOUT1)
#elif	(CPU_NAME == S3C6400)
#define LAYOUT0				(0)		// 8*8
#define LAYOUT1				(1)		// 8*2
#define MATRIX_LAYOUT		(LAYOUT1)
#endif

#endif