wavetimer.tan.rpt

来自「微波炉控制器的设计」· RPT 代码 · 共 284 行 · 第 1/5 页

; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM7128SLC84-15    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                       ; To                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 20.41 MHz ( period = 49.000 ns )                    ; miaobiao:inst2|DCNT6:inst10|CARRY_OUT      ; miaobiao:inst2|DCNT10:inst7|CQI[2]         ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 20.41 MHz ( period = 49.000 ns )                    ; miaobiao:inst2|DCNT6:inst10|CARRY_OUT      ; state_control:inst5|current_state~16       ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 20.41 MHz ( period = 49.000 ns )                    ; miaobiao:inst2|DCNT6:inst10|CARRY_OUT      ; state_control:inst5|current_state~15       ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 20.83 MHz ( period = 48.000 ns )                    ; miaobiao:inst2|DCNT6:inst10|CARRY_OUT      ; miaobiao:inst2|DCNT10:inst7|CQI[3]         ; clk        ; clk      ; None                        ; None                      ; 16.000 ns               ;
; N/A                                     ; 24.39 MHz ( period = 41.000 ns )                    ; miaobiao:inst2|DCNT6:inst10|CARRY_OUT      ; miaobiao:inst2|DCNT10:inst7|CQI[0]         ; clk        ; clk      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 25.00 MHz ( period = 40.000 ns )                    ; miaobiao:inst2|DCNT6:inst10|CARRY_OUT      ; miaobiao:inst2|DCNT10:inst7|CQI[1]         ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 25.00 MHz ( period = 40.000 ns )                    ; miaobiao:inst2|DCNT10:inst9|CARRY_OUT      ; miaobiao:inst2|DCNT10:inst7|CQI[2]         ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 25.00 MHz ( period = 40.000 ns )                    ; miaobiao:inst2|DCNT10:inst9|CARRY_OUT      ; state_control:inst5|current_state~16       ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 25.00 MHz ( period = 40.000 ns )                    ; miaobiao:inst2|DCNT10:inst9|CARRY_OUT      ; state_control:inst5|current_state~15       ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 25.00 MHz ( period = 40.000 ns )                    ; miaobiao:inst2|DCNT6:inst10|CARRY_OUT      ; baojing:inst1|CLKGENBAOJING:inst2|CNT2     ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 25.64 MHz ( period = 39.000 ns )                    ; miaobiao:inst2|DCNT6:inst10|CARRY_OUT      ; miaobiao:inst2|DCNT6:inst8|CQI[2]          ; clk        ; clk      ; None                        ; None                      ; 16.000 ns               ;
; N/A                                     ; 25.64 MHz ( period = 39.000 ns )                    ; miaobiao:inst2|DCNT10:inst9|CARRY_OUT      ; miaobiao:inst2|DCNT10:inst7|CQI[3]         ; clk        ; clk      ; None                        ; None                      ; 16.000 ns               ;
; N/A                                     ; 31.25 MHz ( period = 32.000 ns )                    ; miaobiao:inst2|DCNT10:inst9|CARRY_OUT      ; miaobiao:inst2|DCNT10:inst7|CQI[0]         ; clk        ; clk      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 31.25 MHz ( period = 32.000 ns )                    ; miaobiao:inst2|DCNT6:inst10|CARRY_OUT      ; miaobiao:inst2|DCNT6:inst8|CQI[0]          ; clk        ; clk      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; miaobiao:inst2|DCNT10:inst9|CARRY_OUT      ; miaobiao:inst2|DCNT10:inst7|CQI[1]         ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; miaobiao:inst2|DCNT6:inst8|CARRY_OUT       ; miaobiao:inst2|DCNT10:inst7|CQI[2]         ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; miaobiao:inst2|DCNT6:inst10|CARRY_OUT      ; miaobiao:inst2|DCNT6:inst8|CQI[1]          ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; miaobiao:inst2|DCNT6:inst10|CARRY_OUT      ; miaobiao:inst2|DCNT6:inst8|CQI[3]          ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; miaobiao:inst2|DCNT6:inst8|CARRY_OUT       ; state_control:inst5|current_state~16       ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;