wavetimer.tan.qmsg

微波炉控制器的设计

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 151 " "Warning: Circuit may not operate. Detected 151 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "state_control:inst5\|current_state~15 miaobiao:inst2\|DCNT6:inst10\|CQI\[0\] clk 31.0 ns " "Info: Found hold time violation between source  pin or register \"state_control:inst5\|current_state~15\" and destination pin or register \"miaobiao:inst2\|DCNT6:inst10\|CQI\[0\]\" for clock \"clk\" (Hold time is 31.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "36.000 ns + Largest " "Info: + Largest clock skew is 36.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 39.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 39.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 26 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "" { clk } "NODE_NAME" } "" } } { "wavetimer.bdf" "" { Schematic "E:/EDA实验/wavetimer/wavetimer.bdf" { { 152 280 448 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns miaobiao:inst2\|CLKGEN:inst\|CNTER\[6\] 2 REG LC48 9 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC48; Fanout = 9; REG Node = 'miaobiao:inst2\|CLKGEN:inst\|CNTER\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "1.000 ns" { clk miaobiao:inst2|CLKGEN:inst|CNTER[6] } "NODE_NAME" } "" } } { "CLKGEN.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGEN.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns miaobiao:inst2\|DCNT10:inst7\|CARRY_OUT 3 REG LC41 32 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC41; Fanout = 32; REG Node = 'miaobiao:inst2\|DCNT10:inst7\|CARRY_OUT'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "9.000 ns" { miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT } "NODE_NAME" } "" } } { "DCNT10.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT10.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 22.000 ns miaobiao:inst2\|DCNT6:inst8\|CARRY_OUT 4 REG LC109 32 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC109; Fanout = 32; REG Node = 'miaobiao:inst2\|DCNT6:inst8\|CARRY_OUT'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "9.000 ns" { miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT } "NODE_NAME" } "" } } { "DCNT6.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT6.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 31.000 ns miaobiao:inst2\|DCNT10:inst9\|CARRY_OUT 5 REG LC81 32 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC81; Fanout = 32; REG Node = 'miaobiao:inst2\|DCNT10:inst9\|CARRY_OUT'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "9.000 ns" { miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT } "NODE_NAME" } "" } } { "DCNT10.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT10.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 39.000 ns miaobiao:inst2\|DCNT6:inst10\|CQI\[0\] 6 REG LC93 12 " "Info: 6: + IC(2.000 ns) + CELL(6.000 ns) = 39.000 ns; Loc. = LC93; Fanout = 12; REG Node = 'miaobiao:inst2\|DCNT6:inst10\|CQI\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "8.000 ns" { miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CQI[0] } "NODE_NAME" } "" } } { "DCNT6.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT6.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "31.000 ns ( 79.49 % ) " "Info: Total cell delay = 31.000 ns ( 79.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.000 ns ( 20.51 % ) " "Info: Total interconnect delay = 8.000 ns ( 20.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "39.000 ns" { clk miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CQI[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "39.000 ns" { clk clk~out miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CQI[0] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 26 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "" { clk } "NODE_NAME" } "" } } { "wavetimer.bdf" "" { Schematic "E:/EDA实验/wavetimer/wavetimer.bdf" { { 152 280 448 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns state_control:inst5\|current_state~15 2 REG LC106 169 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC106; Fanout = 169; REG Node = 'state_control:inst5\|current_state~15'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "0.000 ns" { clk state_control:inst5|current_state~15 } "NODE_NAME" } "" } } { "state_control.vhd" "" { Text "E:/EDA实验/wavetimer/state_control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "3.000 ns" { clk state_control:inst5|current_state~15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out state_control:inst5|current_state~15 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "39.000 ns" { clk miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CQI[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "39.000 ns" { clk clk~out miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CQI[0] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "3.000 ns" { clk state_control:inst5|current_state~15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out state_control:inst5|current_state~15 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns - " "Info: - Micro clock to output delay of source is 1.000 ns" {  } { { "state_control.vhd" "" { Text "E:/EDA实验/wavetimer/state_control.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns - Shortest register register " "Info: - Shortest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state_control:inst5\|current_state~15 1 REG LC106 169 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC106; Fanout = 169; REG Node = 'state_control:inst5\|current_state~15'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "" { state_control:inst5|current_state~15 } "NODE_NAME" } "" } } { "state_control.vhd" "" { Text "E:/EDA实验/wavetimer/state_control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns miaobiao:inst2\|DCNT6:inst10\|CQI\[0\] 2 REG LC93 12 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC93; Fanout = 12; REG Node = 'miaobiao:inst2\|DCNT6:inst10\|CQI\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "8.000 ns" { state_control:inst5|current_state~15 miaobiao:inst2|DCNT6:inst10|CQI[0] } "NODE_NAME" } "" } } { "DCNT6.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT6.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "8.000 ns" { state_control:inst5|current_state~15 miaobiao:inst2|DCNT6:inst10|CQI[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { state_control:inst5|current_state~15 miaobiao:inst2|DCNT6:inst10|CQI[0] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "DCNT6.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT6.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "39.000 ns" { clk miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CQI[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "39.000 ns" { clk clk~out miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CQI[0] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "3.000 ns" { clk state_control:inst5|current_state~15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out state_control:inst5|current_state~15 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "8.000 ns" { state_control:inst5|current_state~15 miaobiao:inst2|DCNT6:inst10|CQI[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { state_control:inst5|current_state~15 miaobiao:inst2|DCNT6:inst10|CQI[0] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "state_control:inst5\|current_state~14 idefrost clk 12.000 ns register " "Info: tsu for register \"state_control:inst5\|current_state~14\" (data pin = \"idefrost\", clock pin = \"clk\") is 12.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.000 ns + Longest pin register " "Info: + Longest pin to register delay is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns idefrost 1 PIN PIN_80 30 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_80; Fanout = 30; PIN Node = 'idefrost'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "" { idefrost } "NODE_NAME" } "" } } { "wavetimer.bdf" "" { Schematic "E:/EDA实验/wavetimer/wavetimer.bdf" { { 544 512 680 560 "idefrost" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns state_control:inst5\|current_state~265 2 COMB LC3 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC3; Fanout = 1; COMB Node = 'state_control:inst5\|current_state~265'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "8.000 ns" { idefrost state_control:inst5|current_state~265 } "NODE_NAME" } "" } } { "state_control.vhd" "" { Text "E:/EDA实验/wavetimer/state_control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 11.000 ns state_control:inst5\|current_state~14 3 REG LC4 156 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC4; Fanout = 156; REG Node = 'state_control:inst5\|current_state~14'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "1.000 ns" { state_control:inst5|current_state~265 state_control:inst5|current_state~14 } "NODE_NAME" } "" } } { "state_control.vhd" "" { Text "E:/EDA实验/wavetimer/state_control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 81.82 % ) " "Info: Total cell delay = 9.000 ns ( 81.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 18.18 % ) " "Info: Total interconnect delay = 2.000 ns ( 18.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "11.000 ns" { idefrost state_control:inst5|current_state~265 state_control:inst5|current_state~14 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.000 ns" { idefrost idefrost~out state_control:inst5|current_state~265 state_control:inst5|current_state~14 } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "state_control.vhd" "" { Text "E:/EDA实验/wavetimer/state_control.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 26 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "" { clk } "NODE_NAME" } "" } } { "wavetimer.bdf" "" { Schematic "E:/EDA实验/wavetimer/wavetimer.bdf" { { 152 280 448 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns state_control:inst5\|current_state~14 2 REG LC4 156 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC4; Fanout = 156; REG Node = 'state_control:inst5\|current_state~14'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "0.000 ns" { clk state_control:inst5|current_state~14 } "NODE_NAME" } "" } } { "state_control.vhd" "" { Text "E:/EDA实验/wavetimer/state_control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "3.000 ns" { clk state_control:inst5|current_state~14 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out state_control:inst5|current_state~14 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "11.000 ns" { idefrost state_control:inst5|current_state~265 state_control:inst5|current_state~14 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.000 ns" { idefrost idefrost~out state_control:inst5|current_state~265 state_control:inst5|current_state~14 } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 1.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "3.000 ns" { clk state_control:inst5|current_state~14 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out state_control:inst5|current_state~14 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}