📄 wavetimer.tan.qmsg

📁 微波炉控制器的设计
💻 QMSG
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "wavetimer.bdf" "" { Schematic "E:/EDA实验/wavetimer/wavetimer.bdf" { { 152 280 448 168 "clk" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "25 " "Warning: Found 25 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "miaobiao:inst2\|CLKGEN:inst\|CNTER\[7\] " "Info: Detected ripple clock \"miaobiao:inst2\|CLKGEN:inst\|CNTER\[7\]\" as buffer" {  } { { "CLKGEN.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGEN.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "miaobiao:inst2\|CLKGEN:inst\|CNTER\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "miaobiao:inst2\|CLKGEN:inst\|CNTER\[0\] " "Info: Detected ripple clock \"miaobiao:inst2\|CLKGEN:inst\|CNTER\[0\]\" as buffer" {  } { { "CLKGEN.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGEN.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "miaobiao:inst2\|CLKGEN:inst\|CNTER\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "miaobiao:inst2\|CLKGEN:inst\|CNTER\[1\] " "Info: Detected ripple clock \"miaobiao:inst2\|CLKGEN:inst\|CNTER\[1\]\" as buffer" {  } { { "CLKGEN.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGEN.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "miaobiao:inst2\|CLKGEN:inst\|CNTER\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "miaobiao:inst2\|CLKGEN:inst\|CNTER\[2\] " "Info: Detected ripple clock \"miaobiao:inst2\|CLKGEN:inst\|CNTER\[2\]\" as buffer" {  } { { "CLKGEN.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGEN.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "miaobiao:inst2\|CLKGEN:inst\|CNTER\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "miaobiao:inst2\|CLKGEN:inst\|CNTER\[3\] " "Info: Detected ripple clock \"miaobiao:inst2\|CLKGEN:inst\|CNTER\[3\]\" as buffer" {  } { { "CLKGEN.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGEN.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "miaobiao:inst2\|CLKGEN:inst\|CNTER\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "miaobiao:inst2\|CLKGEN:inst\|CNTER\[4\] " "Info: Detected ripple clock \"miaobiao:inst2\|CLKGEN:inst\|CNTER\[4\]\" as buffer" {  } { { "CLKGEN.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGEN.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "miaobiao:inst2\|CLKGEN:inst\|CNTER\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "miaobiao:inst2\|CLKGEN:inst\|CNTER\[5\] " "Info: Detected ripple clock \"miaobiao:inst2\|CLKGEN:inst\|CNTER\[5\]\" as buffer" {  } { { "CLKGEN.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGEN.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "miaobiao:inst2\|CLKGEN:inst\|CNTER\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "miaobiao:inst2\|CLKGEN:inst\|CNTER\[6\] " "Info: Detected ripple clock \"miaobiao:inst2\|CLKGEN:inst\|CNTER\[6\]\" as buffer" {  } { { "CLKGEN.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGEN.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "miaobiao:inst2\|CLKGEN:inst\|CNTER\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "inputdata:inst3\|QUDOU:inst3\|inst8 " "Info: Detected ripple clock \"inputdata:inst3\|QUDOU:inst3\|inst8\" as buffer" {  } { { "QUDOU.bdf" "" { Schematic "E:/EDA实验/wavetimer/QUDOU.bdf" { { 88 792 856 168 "inst8" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inputdata:inst3\|QUDOU:inst3\|inst8" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "inputdata:inst3\|QUDOU:inst6\|inst8 " "Info: Detected ripple clock \"inputdata:inst3\|QUDOU:inst6\|inst8\" as buffer" {  } { { "QUDOU.bdf" "" { Schematic "E:/EDA实验/wavetimer/QUDOU.bdf" { { 88 792 856 168 "inst8" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inputdata:inst3\|QUDOU:inst6\|inst8" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "inputdata:inst3\|a1_4:inst\|CQ\[0\] " "Info: Detected ripple clock \"inputdata:inst3\|a1_4:inst\|CQ\[0\]\" as buffer" {  } { { "a1_4.vhd" "" { Text "E:/EDA实验/wavetimer/a1_4.vhd" 24 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inputdata:inst3\|a1_4:inst\|CQ\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "inputdata:inst3\|a1_4:inst\|CQ\[1\] " "Info: Detected ripple clock \"inputdata:inst3\|a1_4:inst\|CQ\[1\]\" as buffer" {  } { { "a1_4.vhd" "" { Text "E:/EDA实验/wavetimer/a1_4.vhd" 24 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inputdata:inst3\|a1_4:inst\|CQ\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "miaobiao:inst2\|DCNT10:inst9\|CARRY_OUT " "Info: Detected ripple clock \"miaobiao:inst2\|DCNT10:inst9\|CARRY_OUT\" as buffer" {  } { { "DCNT10.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT10.vhd" 11 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "miaobiao:inst2\|DCNT10:inst9\|CARRY_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "miaobiao:inst2\|DCNT6:inst8\|CARRY_OUT " "Info: Detected ripple clock \"miaobiao:inst2\|DCNT6:inst8\|CARRY_OUT\" as buffer" {  } { { "DCNT6.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT6.vhd" 11 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "miaobiao:inst2\|DCNT6:inst8\|CARRY_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "miaobiao:inst2\|DCNT10:inst7\|CARRY_OUT " "Info: Detected ripple clock \"miaobiao:inst2\|DCNT10:inst7\|CARRY_OUT\" as buffer" {  } { { "DCNT10.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT10.vhd" 11 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "miaobiao:inst2\|DCNT10:inst7\|CARRY_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "baojing:inst1\|CLKGENBAOJING:inst2\|NEWCLK " "Info: Detected ripple clock \"baojing:inst1\|CLKGENBAOJING:inst2\|NEWCLK\" as buffer" {  } { { "CLKGENBAOJING.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGENBAOJING.vhd" 8 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "baojing:inst1\|CLKGENBAOJING:inst2\|NEWCLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[4\] " "Info: Detected ripple clock \"baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[4\]\" as buffer" {  } { { "CLKGENBAOJING.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGENBAOJING.vhd" 18 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[5\] " "Info: Detected ripple clock \"baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[5\]\" as buffer" {  } { { "CLKGENBAOJING.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGENBAOJING.vhd" 18 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[6\] " "Info: Detected ripple clock \"baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[6\]\" as buffer" {  } { { "CLKGENBAOJING.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGENBAOJING.vhd" 18 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[7\] " "Info: Detected ripple clock \"baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[7\]\" as buffer" {  } { { "CLKGENBAOJING.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGENBAOJING.vhd" 18 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[1\] " "Info: Detected ripple clock \"baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[1\]\" as buffer" {  } { { "CLKGENBAOJING.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGENBAOJING.vhd" 18 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[8\] " "Info: Detected ripple clock \"baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[8\]\" as buffer" {  } { { "CLKGENBAOJING.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGENBAOJING.vhd" 18 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[2\] " "Info: Detected ripple clock \"baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[2\]\" as buffer" {  } { { "CLKGENBAOJING.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGENBAOJING.vhd" 18 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[3\] " "Info: Detected ripple clock \"baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[3\]\" as buffer" {  } { { "CLKGENBAOJING.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGENBAOJING.vhd" 18 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[0\] " "Info: Detected ripple clock \"baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[0\]\" as buffer" {  } { { "CLKGENBAOJING.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGENBAOJING.vhd" 18 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "baojing:inst1\|CLKGENBAOJING:inst2\|CNTER\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register miaobiao:inst2\|DCNT6:inst10\|CARRY_OUT register miaobiao:inst2\|DCNT10:inst7\|CQI\[2\] 20.41 MHz 49.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 20.41 MHz between source register \"miaobiao:inst2\|DCNT6:inst10\|CARRY_OUT\" and destination register \"miaobiao:inst2\|DCNT10:inst7\|CQI\[2\]\" (period= 49.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.000 ns + Longest register register " "Info: + Longest register to register delay is 17.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns miaobiao:inst2\|DCNT6:inst10\|CARRY_OUT 1 REG LC89 27 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC89; Fanout = 27; REG Node = 'miaobiao:inst2\|DCNT6:inst10\|CARRY_OUT'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "" { miaobiao:inst2|DCNT6:inst10|CARRY_OUT } "NODE_NAME" } "" } } { "DCNT6.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT6.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns state_control:inst5\|d_miaobiao~155 2 COMB LC105 2 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC105; Fanout = 2; COMB Node = 'state_control:inst5\|d_miaobiao~155'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "9.000 ns" { miaobiao:inst2|DCNT6:inst10|CARRY_OUT state_control:inst5|d_miaobiao~155 } "NODE_NAME" } "" } } { "state_control.vhd" "" { Text "E:/EDA实验/wavetimer/state_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 17.000 ns miaobiao:inst2\|DCNT10:inst7\|CQI\[2\] 3 REG LC46 9 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 17.000 ns; Loc. = LC46; Fanout = 9; REG Node = 'miaobiao:inst2\|DCNT10:inst7\|CQI\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "8.000 ns" { state_control:inst5|d_miaobiao~155 miaobiao:inst2|DCNT10:inst7|CQI[2] } "NODE_NAME" } "" } } { "DCNT10.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT10.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns ( 76.47 % ) " "Info: Total cell delay = 13.000 ns ( 76.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 23.53 % ) " "Info: Total interconnect delay = 4.000 ns ( 23.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "17.000 ns" { miaobiao:inst2|DCNT6:inst10|CARRY_OUT state_control:inst5|d_miaobiao~155 miaobiao:inst2|DCNT10:inst7|CQI[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "17.000 ns" { miaobiao:inst2|DCNT6:inst10|CARRY_OUT state_control:inst5|d_miaobiao~155 miaobiao:inst2|DCNT10:inst7|CQI[2] } { 0.000ns 2.000ns 2.000ns } { 0.000ns 7.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-27.000 ns - Smallest " "Info: - Smallest clock skew is -27.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 26 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "" { clk } "NODE_NAME" } "" } } { "wavetimer.bdf" "" { Schematic "E:/EDA实验/wavetimer/wavetimer.bdf" { { 152 280 448 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns miaobiao:inst2\|CLKGEN:inst\|CNTER\[6\] 2 REG LC48 9 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC48; Fanout = 9; REG Node = 'miaobiao:inst2\|CLKGEN:inst\|CNTER\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "1.000 ns" { clk miaobiao:inst2|CLKGEN:inst|CNTER[6] } "NODE_NAME" } "" } } { "CLKGEN.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGEN.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns miaobiao:inst2\|DCNT10:inst7\|CQI\[2\] 3 REG LC46 9 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC46; Fanout = 9; REG Node = 'miaobiao:inst2\|DCNT10:inst7\|CQI\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "8.000 ns" { miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CQI[2] } "NODE_NAME" } "" } } { "DCNT10.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT10.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "12.000 ns" { clk miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CQI[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CQI[2] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 39.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 39.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 26 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "" { clk } "NODE_NAME" } "" } } { "wavetimer.bdf" "" { Schematic "E:/EDA实验/wavetimer/wavetimer.bdf" { { 152 280 448 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns miaobiao:inst2\|CLKGEN:inst\|CNTER\[6\] 2 REG LC48 9 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC48; Fanout = 9; REG Node = 'miaobiao:inst2\|CLKGEN:inst\|CNTER\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "1.000 ns" { clk miaobiao:inst2|CLKGEN:inst|CNTER[6] } "NODE_NAME" } "" } } { "CLKGEN.vhd" "" { Text "E:/EDA实验/wavetimer/CLKGEN.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns miaobiao:inst2\|DCNT10:inst7\|CARRY_OUT 3 REG LC41 32 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC41; Fanout = 32; REG Node = 'miaobiao:inst2\|DCNT10:inst7\|CARRY_OUT'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "9.000 ns" { miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT } "NODE_NAME" } "" } } { "DCNT10.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT10.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 22.000 ns miaobiao:inst2\|DCNT6:inst8\|CARRY_OUT 4 REG LC109 32 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC109; Fanout = 32; REG Node = 'miaobiao:inst2\|DCNT6:inst8\|CARRY_OUT'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "9.000 ns" { miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT } "NODE_NAME" } "" } } { "DCNT6.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT6.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 31.000 ns miaobiao:inst2\|DCNT10:inst9\|CARRY_OUT 5 REG LC81 32 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC81; Fanout = 32; REG Node = 'miaobiao:inst2\|DCNT10:inst9\|CARRY_OUT'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "9.000 ns" { miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT } "NODE_NAME" } "" } } { "DCNT10.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT10.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 39.000 ns miaobiao:inst2\|DCNT6:inst10\|CARRY_OUT 6 REG LC89 27 " "Info: 6: + IC(2.000 ns) + CELL(6.000 ns) = 39.000 ns; Loc. = LC89; Fanout = 27; REG Node = 'miaobiao:inst2\|DCNT6:inst10\|CARRY_OUT'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "8.000 ns" { miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CARRY_OUT } "NODE_NAME" } "" } } { "DCNT6.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT6.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "31.000 ns ( 79.49 % ) " "Info: Total cell delay = 31.000 ns ( 79.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.000 ns ( 20.51 % ) " "Info: Total interconnect delay = 8.000 ns ( 20.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "39.000 ns" { clk miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CARRY_OUT } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "39.000 ns" { clk clk~out miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CARRY_OUT } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "12.000 ns" { clk miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CQI[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CQI[2] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "39.000 ns" { clk miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CARRY_OUT } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "39.000 ns" { clk clk~out miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CARRY_OUT } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "DCNT6.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT6.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "DCNT10.vhd" "" { Text "E:/EDA实验/wavetimer/DCNT10.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "17.000 ns" { miaobiao:inst2|DCNT6:inst10|CARRY_OUT state_control:inst5|d_miaobiao~155 miaobiao:inst2|DCNT10:inst7|CQI[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "17.000 ns" { miaobiao:inst2|DCNT6:inst10|CARRY_OUT state_control:inst5|d_miaobiao~155 miaobiao:inst2|DCNT10:inst7|CQI[2] } { 0.000ns 2.000ns 2.000ns } { 0.000ns 7.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "12.000 ns" { clk miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CQI[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CQI[2] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "wavetimer" "UNKNOWN" "V1" "E:/EDA实验/wavetimer/db/wavetimer.quartus_db" { Floorplan "E:/EDA实验/wavetimer/" "" "39.000 ns" { clk miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CARRY_OUT } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "39.000 ns" { clk clk~out miaobiao:inst2|CLKGEN:inst|CNTER[6] miaobiao:inst2|DCNT10:inst7|CARRY_OUT miaobiao:inst2|DCNT6:inst8|CARRY_OUT miaobiao:inst2|DCNT10:inst9|CARRY_OUT miaobiao:inst2|DCNT6:inst10|CARRY_OUT } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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