a1_4.vhd

微波炉控制器的设计

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_UNSIGNED.all;
ENTITY a1_4 IS

	PORT
	(
		in1 : IN BIT;
		kz : IN BIT;
		our1 : OUT BIT;
		our2 : OUT BIT;
		our3 : OUT BIT;
		our4 : OUT BIT
	);

	
END a1_4;
ARCHITECTURE block_name_architecture OF a1_4 IS	
SIGNAL CQ :STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
--CQ<="00";
PROCESS(kz)	
BEGIN
IF (kz'event AND kz='1') THEN CQ<=CQ + 1;
ELSE CQ<=CQ;
END IF;
END PROCESS;
PROCESS(CQ)
BEGIN 
--IF    CQ="00" THEN  our1<=in1;
--	else
--ELSIF CQ="01" THEN  our2<=in1;
--ELSIF CQ="10" THEN  our3<=in1;

--ELSE our4<=in1;
--END IF;
	CASE CQ IS
	WHEN "00"=>our1<=in1;our2<='0';our3<='0';our4<='0';
	WHEN "01"=>our1<='0';our2<=in1;our3<='0';our4<='0';
	WHEN "10"=>our1<='0';our2<='0';our3<=in1;our4<='0';
	WHEN others=>our1<='0';our2<='0';our3<='0';our4<=in1;
	END CASE;
END PROCESS;
END block_name_architecture;