wavetimer.map.rpt

微波炉控制器的设计

; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                             ;
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Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


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; Analysis & Synthesis Equations ;
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The equations can be found in E:/EDA实验/wavetimer/wavetimer.map.eqn.


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; Analysis & Synthesis Messages ;
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Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Mon May 26 16:39:36 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off wavetimer -c wavetimer
Info: Found 1 design units, including 1 entities, in source file wavetimer.bdf
    Info: Found entity 1: wavetimer
Info: Found 2 design units, including 1 entities, in source file state_control.vhd
    Info: Found design unit 1: state_control-ART
    Info: Found entity 1: state_control
Info: Found 1 design units, including 1 entities, in source file QUDOU.bdf
    Info: Found entity 1: QUDOU
Info: Elaborating entity "wavetimer" for the top level hierarchy
Warning: Using design file baojing.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: baojing
Info: Elaborating entity "baojing" for hierarchy "baojing:inst1"
Warning: Using design file CLKGENBAOJING.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: CLKGENBAOJING-ART
    Info: Found entity 1: CLKGENBAOJING
Info: Elaborating entity "CLKGENBAOJING" for hierarchy "baojing:inst1|CLKGENBAOJING:inst2"
Warning: Using design file CNT3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: CNT3-ART
    Info: Found entity 1: CNT3
Info: Elaborating entity "CNT3" for hierarchy "baojing:inst1|CNT3:inst4"
Info: Elaborating entity "state_control" for hierarchy "state_control:inst5"
Info (10425): VHDL Case Statement information at state_control.vhd(59): OTHERS choice is never selected
Warning: Using design file miaobiao.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: miaobiao
Info: Elaborating entity "miaobiao" for hierarchy "miaobiao:inst2"
Warning: Primitive "AND3" of instance "inst1" not used
Warning: Using design file DCNT6.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: DCNT6-ART
    Info: Found entity 1: DCNT6
Info: Elaborating entity "DCNT6" for hierarchy "miaobiao:inst2|DCNT6:inst10"
Warning (10492): VHDL Process Statement warning at DCNT6.vhd(19): signal "DATAIN" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Using design file DCNT10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: DCNT10-ART
    Info: Found entity 1: DCNT10
Info: Elaborating entity "DCNT10" for hierarchy "miaobiao:inst2|DCNT10:inst9"
Warning: Using design file CLKGEN.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: CLKGEN-ART
    Info: Found entity 1: CLKGEN
Info: Elaborating entity "CLKGEN" for hierarchy "miaobiao:inst2|CLKGEN:inst"
Warning: Using design file inputdata.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: inputdata
Info: Elaborating entity "inputdata" for hierarchy "inputdata:inst3"
Warning: Using design file CNT6.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: CNT6-ART
    Info: Found entity 1: CNT6
Info: Elaborating entity "CNT6" for hierarchy "inputdata:inst3|CNT6:inst5"
Warning: Using design file a1_4.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: a1_4-block_name_architecture
    Info: Found entity 1: a1_4
Info: Elaborating entity "a1_4" for hierarchy "inputdata:inst3|a1_4:inst"
Warning (10492): VHDL Process Statement warning at a1_4.vhd(25): signal "CQ" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at a1_4.vhd(38): signal "in1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at a1_4.vhd(39): signal "in1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at a1_4.vhd(40): signal "in1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at a1_4.vhd(41): signal "in1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "QUDOU" for hierarchy "inputdata:inst3|QUDOU:inst3"
Warning: Using design file CNT10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: CNT10-ART
    Info: Found entity 1: CNT10
Info: Elaborating entity "CNT10" for hierarchy "inputdata:inst3|CNT10:inst4"
Warning: Using design file workchoose.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: workchoose
Info: Elaborating entity "workchoose" for hierarchy "workchoose:inst"
Warning: Using design file mux3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: mux3-a
    Info: Found entity 1: mux3
Info: Elaborating entity "mux3" for hierarchy "workchoose:inst|mux3:inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: State machine "|wavetimer|state_control:inst5|current_state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|wavetimer|state_control:inst5|current_state"
Info: Encoding result for state machine "|wavetimer|state_control:inst5|current_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "state_control:inst5|current_state~16"
        Info: Encoded state bit "state_control:inst5|current_state~15"
        Info: Encoded state bit "state_control:inst5|current_state~14"
    Info: State "|wavetimer|state_control:inst5|current_state.idle" uses code string "000"
    Info: State "|wavetimer|state_control:inst5|current_state.st1_set" uses code string "001"
    Info: State "|wavetimer|state_control:inst5|current_state.st2_miaobiao" uses code string "010"
    Info: State "|wavetimer|state_control:inst5|current_state.st3_pause" uses code string "011"
    Info: State "|wavetimer|state_control:inst5|current_state.st4_done" uses code string "100"
Info: Ignored 16 buffer(s)
    Info: Ignored 16 SOFT buffer(s)
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 156 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 20 output pins
    Info: Implemented 115 macrocells
    Info: Implemented 11 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings
    Info: Processing ended: Mon May 26 16:39:55 2008
    Info: Elapsed time: 00:00:20