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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY state_control IS
PORT(CLK,RESET,START,STOP,DONE:IN STD_LOGIC;
LD_COOK,LD_ENA,LD_LOAD,LD_DONE,LD_CLR:OUT STD_LOGIC);
END ENTITY state_control;
ARCHITECTURE ART OF state_control IS
TYPE STATE_TYPE IS(IDLE,LAMP_START,SET_STOP,DONE_MSG);
SIGNAL NXT_STATE,CURR_STATE:STATE_TYPE;
BEGIN
PROCESS(CLK,RESET)IS
BEGIN
IF RESET='1' THEN
CURR_STATE<=IDLE;
ELSIF CLK'EVENT AND CLK='1'THEN
CURR_STATE<=NXT_STATE;
END IF;
END PROCESS;
PROCESS(CURR_STATE,START,STOP,DONE)IS
BEGIN
--NXT_STATE<=STA; --DEFAULT NEXT STATE IS IDLE;
LD_COOK<='0';
LD_ENA<='0';
--LD_STOP<='0';
LD_DONE<='0';
LD_CLR<='0';
CASE CURR_STATE IS
--WHEN STA=>
-- IF (START='1'AND RESET='1') THEN
-- CURR_STATE <=IDLE;
-- ELSE
-- CURR_STATE <=STA;
--END IF;
WHEN IDLE=>
--LD_DONE<='0';
IF(START='1')THEN
NXT_STATE<=LAMP_START;
ELSIF(START='0')THEN
LD_COOK<='0';
LD_ENA<='1';
LD_LOAD<='1';
LD_CLR<='0';
END IF;
WHEN LAMP_START=>
LD_COOK<='1';
LD_LOAD<='0';
LD_ENA<='0';
LD_CLR<='0';
IF(STOP='1'and start='1') THEN
NXT_STATE<=SET_STOP;
elsIF (DONE='1') THEN
NXT_STATE<=DONE_MSG;
else
NXT_STATE<=LAMP_START;
END IF;
WHEN SET_STOP=>
LD_COOK<='0';
LD_LOAD<='0';
LD_ENA<='0';
LD_CLR<='0';
IF(STOP='1') THEN
NXT_STATE<=SET_STOP;
ELSE
NXT_STATE<=LAMP_START;
END IF;
WHEN DONE_MSG=>
LD_CLR<='1';
LD_COOK<='0';
LD_DONE<='1';
NXT_STATE<=IDLE;
END CASE;
END PROCESS;
END ARCHITECTURE ART;
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