📄 wavetimer.sim.rpt
字号:
; |wavetimer|miaobiao:inst2|DCNT10:inst9|CQI[1]~309 ; |wavetimer|miaobiao:inst2|DCNT10:inst9|CQI[1]~309 ; pexpout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst9|CQI[2]~314 ; |wavetimer|miaobiao:inst2|DCNT10:inst9|CQI[2]~314 ; pexpout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst9|CQI[2]~320 ; |wavetimer|miaobiao:inst2|DCNT10:inst9|CQI[2]~320 ; pexpout ;
; |wavetimer|miaobiao:inst2|DCNT6:inst10|CQI[0]~294 ; |wavetimer|miaobiao:inst2|DCNT6:inst10|CQI[0]~294 ; pexpout ;
; |wavetimer|miaobiao:inst2|DCNT6:inst10|CQI[1]~297 ; |wavetimer|miaobiao:inst2|DCNT6:inst10|CQI[1]~297 ; pexpout ;
; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|CNT2~16 ; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|CNT2~16 ; pexpout ;
; |wavetimer|state_control:inst5|next_state.idle~130sexp ; |wavetimer|state_control:inst5|next_state.idle~130sexp ; dataout ;
; |wavetimer|rtl~196sexp ; |wavetimer|rtl~196sexp ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~133sexp1 ; |wavetimer|state_control:inst5|next_state.idle~133sexp1 ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~133sexp2 ; |wavetimer|state_control:inst5|next_state.idle~133sexp2 ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI~297sexp1 ; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI~297sexp1 ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI~297sexp2 ; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI~297sexp2 ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI~297sexp3 ; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI~297sexp3 ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI~297sexp4 ; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI~297sexp4 ; dataout ;
; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|process2~32bal ; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|process2~32bal ; dataout ;
; |wavetimer|clear ; |wavetimer|clear ; dataout ;
; |wavetimer|dooropen ; |wavetimer|dooropen ; dataout ;
; |wavetimer|icook ; |wavetimer|icook ; dataout ;
; |wavetimer|idefrost ; |wavetimer|idefrost ; dataout ;
; |wavetimer|ibake ; |wavetimer|ibake ; dataout ;
; |wavetimer|S[0] ; |wavetimer|S[0] ; padio ;
; |wavetimer|S[1] ; |wavetimer|S[1] ; padio ;
; |wavetimer|S[2] ; |wavetimer|S[2] ; padio ;
; |wavetimer|S[3] ; |wavetimer|S[3] ; padio ;
; |wavetimer|10S[0] ; |wavetimer|10S[0] ; padio ;
; |wavetimer|10S[1] ; |wavetimer|10S[1] ; padio ;
; |wavetimer|10S[2] ; |wavetimer|10S[2] ; padio ;
; |wavetimer|10S[3] ; |wavetimer|10S[3] ; padio ;
; |wavetimer|MIN[0] ; |wavetimer|MIN[0] ; padio ;
; |wavetimer|MIN[1] ; |wavetimer|MIN[1] ; padio ;
; |wavetimer|MIN[2] ; |wavetimer|MIN[2] ; padio ;
; |wavetimer|MIN[3] ; |wavetimer|MIN[3] ; padio ;
; |wavetimer|10MIN[0] ; |wavetimer|10MIN[0] ; padio ;
; |wavetimer|10MIN[1] ; |wavetimer|10MIN[1] ; padio ;
; |wavetimer|10MIN[2] ; |wavetimer|10MIN[2] ; padio ;
; |wavetimer|10MIN[3] ; |wavetimer|10MIN[3] ; padio ;
; |wavetimer|done ; |wavetimer|done ; padio ;
; |wavetimer|state_control:inst5|next_state.idle~149 ; |wavetimer|state_control:inst5|next_state.idle~149 ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~150 ; |wavetimer|state_control:inst5|next_state.idle~150 ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~151 ; |wavetimer|state_control:inst5|next_state.idle~151 ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~152 ; |wavetimer|state_control:inst5|next_state.idle~152 ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~153 ; |wavetimer|state_control:inst5|next_state.idle~153 ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~154 ; |wavetimer|state_control:inst5|next_state.idle~154 ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~155 ; |wavetimer|state_control:inst5|next_state.idle~155 ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~156 ; |wavetimer|state_control:inst5|next_state.idle~156 ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~157 ; |wavetimer|state_control:inst5|next_state.idle~157 ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~158 ; |wavetimer|state_control:inst5|next_state.idle~158 ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~159 ; |wavetimer|state_control:inst5|next_state.idle~159 ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~160 ; |wavetimer|state_control:inst5|next_state.idle~160 ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI[3]~322 ; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI[3]~322 ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI[3]~323 ; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI[3]~323 ; dataout ;
+-------------------------------------------------------------+-------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+-------------------------------------------------------------+-------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------------------------------------+-------------------------------------------------------------+------------------+
; |wavetimer|baojing:inst1|CNT3:inst4|CQI[0] ; |wavetimer|baojing:inst1|CNT3:inst4|CQI[0] ; dataout ;
; |wavetimer|baojing:inst1|CNT3:inst4|CQI[1] ; |wavetimer|baojing:inst1|CNT3:inst4|CQI[1] ; dataout ;
; |wavetimer|inputdata:inst3|a1_4:inst|CQ[0] ; |wavetimer|inputdata:inst3|a1_4:inst|CQ[0] ; dataout ;
; |wavetimer|inputdata:inst3|a1_4:inst|CQ[1] ; |wavetimer|inputdata:inst3|a1_4:inst|CQ[1] ; dataout ;
; |wavetimer|baojing:inst1|CNT3:inst4|CQI[3] ; |wavetimer|baojing:inst1|CNT3:inst4|CQI[3] ; dataout ;
; |wavetimer|inputdata:inst3|CNT6:inst5|CQI[0] ; |wavetimer|inputdata:inst3|CNT6:inst5|CQI[0] ; dataout ;
; |wavetimer|state_control:inst5|next_state.idle~128 ; |wavetimer|state_control:inst5|next_state.idle~128 ; dataout ;
; |wavetimer|inputdata:inst3|CNT6:inst2|CQI[0] ; |wavetimer|inputdata:inst3|CNT6:inst2|CQI[0] ; dataout ;
; |wavetimer|inputdata:inst3|CNT10:inst4|CQI[0] ; |wavetimer|inputdata:inst3|CNT10:inst4|CQI[0] ; dataout ;
; |wavetimer|inputdata:inst3|CNT10:inst1|CQI[0] ; |wavetimer|inputdata:inst3|CNT10:inst1|CQI[0] ; dataout ;
; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|CNTER[6] ; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|CNTER[6] ; dataout ;
; |wavetimer|inputdata:inst3|CNT10:inst4|CQI[2] ; |wavetimer|inputdata:inst3|CNT10:inst4|CQI[2] ; dataout ;
; |wavetimer|inputdata:inst3|CNT10:inst1|CQI[2] ; |wavetimer|inputdata:inst3|CNT10:inst1|CQI[2] ; dataout ;
; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|CNTER[7] ; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|CNTER[7] ; dataout ;
; |wavetimer|inputdata:inst3|CNT6:inst5|CQI[3] ; |wavetimer|inputdata:inst3|CNT6:inst5|CQI[3] ; dataout ;
; |wavetimer|inputdata:inst3|CNT6:inst2|CQI[3] ; |wavetimer|inputdata:inst3|CNT6:inst2|CQI[3] ; dataout ;
; |wavetimer|inputdata:inst3|CNT10:inst4|CQI[3] ; |wavetimer|inputdata:inst3|CNT10:inst4|CQI[3] ; dataout ;
; |wavetimer|inputdata:inst3|CNT10:inst1|CQI[3] ; |wavetimer|inputdata:inst3|CNT10:inst1|CQI[3] ; dataout ;
; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|CNTER[8] ; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|CNTER[8] ; dataout ;
; |wavetimer|inputdata:inst3|CNT6:inst5|CQI[1] ; |wavetimer|inputdata:inst3|CNT6:inst5|CQI[1] ; dataout ;
; |wavetimer|inputdata:inst3|CNT6:inst2|CQI[1] ; |wavetimer|inputdata:inst3|CNT6:inst2|CQI[1] ; dataout ;
; |wavetimer|inputdata:inst3|CNT10:inst4|CQI[1] ; |wavetimer|inputdata:inst3|CNT10:inst4|CQI[1] ; dataout ;
; |wavetimer|inputdata:inst3|CNT10:inst1|CQI[1] ; |wavetimer|inputdata:inst3|CNT10:inst1|CQI[1] ; dataout ;
; |wavetimer|miaobiao:inst2|CLKGEN:inst|CNTER[6] ; |wavetimer|miaobiao:inst2|CLKGEN:inst|CNTER[6] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI[0] ; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI[0] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI[1] ; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI[1] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI[3]~305 ; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI[3]~305 ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI[3] ; |wavetimer|miaobiao:inst2|DCNT10:inst7|CQI[3] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst7|CARRY_OUT ; |wavetimer|miaobiao:inst2|DCNT10:inst7|CARRY_OUT ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT6:inst8|CQI[0] ; |wavetimer|miaobiao:inst2|DCNT6:inst8|CQI[0] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT6:inst8|CQI[1] ; |wavetimer|miaobiao:inst2|DCNT6:inst8|CQI[1] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT6:inst8|CQI[2] ; |wavetimer|miaobiao:inst2|DCNT6:inst8|CQI[2] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT6:inst8|CARRY_OUT ; |wavetimer|miaobiao:inst2|DCNT6:inst8|CARRY_OUT ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst9|CQI[0] ; |wavetimer|miaobiao:inst2|DCNT10:inst9|CQI[0] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst9|CQI[1] ; |wavetimer|miaobiao:inst2|DCNT10:inst9|CQI[1] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst9|CQI[3] ; |wavetimer|miaobiao:inst2|DCNT10:inst9|CQI[3] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT10:inst9|CARRY_OUT ; |wavetimer|miaobiao:inst2|DCNT10:inst9|CARRY_OUT ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT6:inst10|CQI[0] ; |wavetimer|miaobiao:inst2|DCNT6:inst10|CQI[0] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT6:inst10|CQI[1] ; |wavetimer|miaobiao:inst2|DCNT6:inst10|CQI[1] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT6:inst10|CQI[2] ; |wavetimer|miaobiao:inst2|DCNT6:inst10|CQI[2] ; dataout ;
; |wavetimer|miaobiao:inst2|DCNT6:inst10|CARRY_OUT ; |wavetimer|miaobiao:inst2|DCNT6:inst10|CARRY_OUT ; dataout ;
; |wavetimer|state_control:inst5|current_state~15 ; |wavetimer|state_control:inst5|current_state~15 ; dataout ;
; |wavetimer|state_control:inst5|current_state~16 ; |wavetimer|state_control:inst5|current_state~16 ; dataout ;
; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|CNT2 ; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|CNT2 ; dataout ;
; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|NEWCLK ; |wavetimer|baojing:inst1|CLKGENBAOJING:inst2|NEWCLK ; dataout ;
; |wavetimer|state_control:inst5|next_state.st4_done~30 ; |wavetimer|state_control:inst5|next_state.st4_done~30 ; dataout ;
; |wavetimer|state_control:inst5|current_state~265 ; |wavetimer|state_control:inst5|current_state~265 ; pexpout ;
; |wavetimer|inputdata:inst3|CNT6:inst5|CQI[0]~105 ; |wavetimer|inputdata:inst3|CNT6:inst5|CQI[0]~105 ; pexpout ;
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