state_control.vhd

微波炉控制器的设计

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_ARITH.ALL;
ENTITY state_control IS
   PORT(clk,clear,start,pause,done,dooropen,choose_en : IN std_logic;
   		d_load,d_miaobiao,enout,clearout,DONEOUT: OUT std_logic);
END ENTITY state_control;
ARCHITECTURE ART OF state_control IS
  TYPE STATE_TYPE IS(idle,st1_set,st2_miaobiao,st3_pause,st4_done);
SIGNAL next_state,current_state:STATE_TYPE;
BEGIN
PROCESS(clk,clear)
 BEGIN
        if clear='1' then   current_state<=idle;
      elsif clk'EVENT and clk='1'then
         current_state<=next_state;
    end if;
END PROCESS;
PROCESS(current_state,start,pause,done,dooropen,choose_en,clear)IS
  BEGIN    
  CASE current_state IS
	when idle=>			if choose_en='1' then 
	                    d_load<='0';
	         			enout<='1';	
						clearout<='0'; 
						DONEOUT<='0'; 
						d_miaobiao <='0';   	          
        			    next_state <= st1_set; 
					    else 
	         		 	d_load<='0';
	         			enout<='0';	
						d_miaobiao <='0'; 
						DONEOUT<='0'; 
						clearout<='1';   
						next_state <= idle;        			
	                    end if;  
    when st1_set => if start='1' then  
                    d_miaobiao <='1'; DONEOUT<='0'; d_load<='0'; clearout<='0'; enout<='0';         
                    next_state <= st2_miaobiao;
                    elsif clear='1' then 
                    clearout<='1';DONEOUT<='0';d_load<='0'; enout<='0'; d_miaobiao <='0';        
                    next_state <= idle;
                    else  d_load<='1';DONEOUT<='0'; enout<='1';clearout<='0';d_miaobiao <='0'; 
					next_state <=st1_set;
                    end if; 
	when st2_miaobiao => 
						 if pause='1' then clearout<='0'; DONEOUT<='0'; DONEOUT<='0';  enout<='0';d_load<='0';d_miaobiao<='0'; 
                         next_state <= st3_pause; 
                         elsif  done='1' then DONEOUT<='1'; d_miaobiao <='0'; d_load<='0';clearout<='0'; enout<='0';next_state <= st4_done;                  	  
                         else  d_miaobiao <='1'; DONEOUT<='0'; d_load<='0'; clearout<='0'; enout<='0'; next_state <= st2_miaobiao;  end if;     
    
	 when st3_pause => if pause='0' then d_miaobiao <='1'; DONEOUT<='0';  d_load<='0';  clearout<='0'; enout<='0';         
                       next_state <= st2_miaobiao;
                       else  d_load<='0'; d_miaobiao<='0'; DONEOUT<='0';  clearout<='0'; enout<='0'; next_state <=st3_pause;
                       end if;  
      when st4_done => d_load<='0';enout<='0';d_miaobiao <='0';
                       if dooropen='1' then   DONEOUT<='0';clearout<='1';d_miaobiao <='0'; enout<='0';d_load<='1'; next_state <= idle; 
					   else DONEOUT<='1';clearout<='0';d_miaobiao <='0'; enout<='0';d_load<='0'; next_state <=st4_done; end if;
      when others=> next_state <= idle;
       END CASE;
  END PROCESS;
 END ARCHITECTURE ART;