wavetimer.tan.talkback.xml

微波炉控制器的设计

<!--
This XML file (created on Mon May 26 16:40:15 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>a0000004aa7b</host_id>
	<nic_id>a0000004aa7b</nic_id>
	<cdrive_id>e019214b</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Mon May 26 16:40:15 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1099</cpu_freq>
	</cpu>
	<ram units="MB">255</ram>
</machine>
<top_file>E:/EDA实验/wavetimer/wavetimer</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off wavetimer -c wavetimer</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Circuit may not operate. Detected 151 non-operational path(s) clocked by clock &quot;clk&quot; with clock skew larger than data delay. See Compilation Report for details.</warning>
	<warning>Warning: Found 25 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<warning>Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings</info>
	<info>Info: Elapsed time: 00:00:02</info>
	<info>Info: Processing ended: Mon May 26 16:40:14 2008</info>
	<info>Info: th for register &quot;miaobiao:inst2|DCNT6:inst10|CQI[3]&quot; (data pin = &quot;stop&quot;, clock pin = &quot;clk&quot;) is 33.000 ns</info>
	<info>Info: - Shortest pin to register delay is 10.000 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>12.000 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>53.000 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tpd</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>15.000 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>33.000 ns</actual>
	</nonclk>
	<clk>
		<name>clk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>20.41 MHz ( period = 49.000 ns )</actual>
	</clk>
</performance>
<compile_id>92C15EDC</compile_id>
</talkback>