fft.hier_info

利用FPGA的IP核来实现fft的设计

|fft
clock_c => clock_c~0.IN1
enable_i => enable_i~0.IN1
reset_i => reset_i~0.IN1
sync_i => sync_i~0.IN1
data_0_i[0] => data_0_i[0]~15.IN1
data_0_i[1] => data_0_i[1]~14.IN1
data_0_i[2] => data_0_i[2]~13.IN1
data_0_i[3] => data_0_i[3]~12.IN1
data_0_i[4] => data_0_i[4]~11.IN1
data_0_i[5] => data_0_i[5]~10.IN1
data_0_i[6] => data_0_i[6]~9.IN1
data_0_i[7] => data_0_i[7]~8.IN1
data_0_i[8] => data_0_i[8]~7.IN1
data_0_i[9] => data_0_i[9]~6.IN1
data_0_i[10] => data_0_i[10]~5.IN1
data_0_i[11] => data_0_i[11]~4.IN1
data_0_i[12] => data_0_i[12]~3.IN1
data_0_i[13] => data_0_i[13]~2.IN1
data_0_i[14] => data_0_i[14]~1.IN1
data_0_i[15] => data_0_i[15]~0.IN1
data_1_i[0] => data_1_i[0]~15.IN1
data_1_i[1] => data_1_i[1]~14.IN1
data_1_i[2] => data_1_i[2]~13.IN1
data_1_i[3] => data_1_i[3]~12.IN1
data_1_i[4] => data_1_i[4]~11.IN1
data_1_i[5] => data_1_i[5]~10.IN1
data_1_i[6] => data_1_i[6]~9.IN1
data_1_i[7] => data_1_i[7]~8.IN1
data_1_i[8] => data_1_i[8]~7.IN1
data_1_i[9] => data_1_i[9]~6.IN1
data_1_i[10] => data_1_i[10]~5.IN1
data_1_i[11] => data_1_i[11]~4.IN1
data_1_i[12] => data_1_i[12]~3.IN1
data_1_i[13] => data_1_i[13]~2.IN1
data_1_i[14] => data_1_i[14]~1.IN1
data_1_i[15] => data_1_i[15]~0.IN1
sync_o <= cf_fft_1024_8:fft2.sync_o
data_0_o[0] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[1] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[2] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[3] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[4] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[5] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[6] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[7] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[8] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[9] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[10] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[11] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[12] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[13] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[14] <= cf_fft_1024_8:fft2.data_0_o
data_0_o[15] <= cf_fft_1024_8:fft2.data_0_o
data_1_o[0] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[1] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[2] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[3] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[4] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[5] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[6] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[7] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[8] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[9] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[10] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[11] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[12] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[13] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[14] <= cf_fft_1024_8:fft2.data_1_o
data_1_o[15] <= cf_fft_1024_8:fft2.data_1_o


|fft|cf_fft_1024_8:fft2
clock_c => clock_c~0.IN1
enable_i => enable_i~0.IN1
reset_i => reset_i~0.IN1
sync_i => sync_i~0.IN1
data_0_i[0] => data_0_i[0]~15.IN1
data_0_i[1] => data_0_i[1]~14.IN1
data_0_i[2] => data_0_i[2]~13.IN1
data_0_i[3] => data_0_i[3]~12.IN1
data_0_i[4] => data_0_i[4]~11.IN1
data_0_i[5] => data_0_i[5]~10.IN1
data_0_i[6] => data_0_i[6]~9.IN1
data_0_i[7] => data_0_i[7]~8.IN1
data_0_i[8] => data_0_i[8]~7.IN1
data_0_i[9] => data_0_i[9]~6.IN1
data_0_i[10] => data_0_i[10]~5.IN1
data_0_i[11] => data_0_i[11]~4.IN1
data_0_i[12] => data_0_i[12]~3.IN1
data_0_i[13] => data_0_i[13]~2.IN1
data_0_i[14] => data_0_i[14]~1.IN1
data_0_i[15] => data_0_i[15]~0.IN1
data_1_i[0] => data_1_i[0]~15.IN1
data_1_i[1] => data_1_i[1]~14.IN1
data_1_i[2] => data_1_i[2]~13.IN1
data_1_i[3] => data_1_i[3]~12.IN1
data_1_i[4] => data_1_i[4]~11.IN1
data_1_i[5] => data_1_i[5]~10.IN1
data_1_i[6] => data_1_i[6]~9.IN1
data_1_i[7] => data_1_i[7]~8.IN1
data_1_i[8] => data_1_i[8]~7.IN1
data_1_i[9] => data_1_i[9]~6.IN1
data_1_i[10] => data_1_i[10]~5.IN1
data_1_i[11] => data_1_i[11]~4.IN1
data_1_i[12] => data_1_i[12]~3.IN1
data_1_i[13] => data_1_i[13]~2.IN1
data_1_i[14] => data_1_i[14]~1.IN1
data_1_i[15] => data_1_i[15]~0.IN1
sync_o <= cf_fft_1024_8_1:s1.port6
data_0_o[0] <= cf_fft_1024_8_1:s1.port7
data_0_o[1] <= cf_fft_1024_8_1:s1.port7
data_0_o[2] <= cf_fft_1024_8_1:s1.port7
data_0_o[3] <= cf_fft_1024_8_1:s1.port7
data_0_o[4] <= cf_fft_1024_8_1:s1.port7
data_0_o[5] <= cf_fft_1024_8_1:s1.port7
data_0_o[6] <= cf_fft_1024_8_1:s1.port7
data_0_o[7] <= cf_fft_1024_8_1:s1.port7
data_0_o[8] <= cf_fft_1024_8_1:s1.port7
data_0_o[9] <= cf_fft_1024_8_1:s1.port7
data_0_o[10] <= cf_fft_1024_8_1:s1.port7
data_0_o[11] <= cf_fft_1024_8_1:s1.port7
data_0_o[12] <= cf_fft_1024_8_1:s1.port7
data_0_o[13] <= cf_fft_1024_8_1:s1.port7
data_0_o[14] <= cf_fft_1024_8_1:s1.port7
data_0_o[15] <= cf_fft_1024_8_1:s1.port7
data_1_o[0] <= cf_fft_1024_8_1:s1.port8
data_1_o[1] <= cf_fft_1024_8_1:s1.port8
data_1_o[2] <= cf_fft_1024_8_1:s1.port8
data_1_o[3] <= cf_fft_1024_8_1:s1.port8
data_1_o[4] <= cf_fft_1024_8_1:s1.port8
data_1_o[5] <= cf_fft_1024_8_1:s1.port8
data_1_o[6] <= cf_fft_1024_8_1:s1.port8
data_1_o[7] <= cf_fft_1024_8_1:s1.port8
data_1_o[8] <= cf_fft_1024_8_1:s1.port8
data_1_o[9] <= cf_fft_1024_8_1:s1.port8
data_1_o[10] <= cf_fft_1024_8_1:s1.port8
data_1_o[11] <= cf_fft_1024_8_1:s1.port8
data_1_o[12] <= cf_fft_1024_8_1:s1.port8
data_1_o[13] <= cf_fft_1024_8_1:s1.port8
data_1_o[14] <= cf_fft_1024_8_1:s1.port8
data_1_o[15] <= cf_fft_1024_8_1:s1.port8


|fft|cf_fft_1024_8:fft2|cf_fft_1024_8_1:s1
clock_c => clock_c~0.IN4
i1 => i1~0.IN1
i2[0] => i2[0]~15.IN1
i2[1] => i2[1]~14.IN1
i2[2] => i2[2]~13.IN1
i2[3] => i2[3]~12.IN1
i2[4] => i2[4]~11.IN1
i2[5] => i2[5]~10.IN1
i2[6] => i2[6]~9.IN1
i2[7] => i2[7]~8.IN1
i2[8] => i2[8]~7.IN1
i2[9] => i2[9]~6.IN1
i2[10] => i2[10]~5.IN1
i2[11] => i2[11]~4.IN1
i2[12] => i2[12]~3.IN1
i2[13] => i2[13]~2.IN1
i2[14] => i2[14]~1.IN1
i2[15] => i2[15]~0.IN1
i3[0] => i3[0]~15.IN1
i3[1] => i3[1]~14.IN1
i3[2] => i3[2]~13.IN1
i3[3] => i3[3]~12.IN1
i3[4] => i3[4]~11.IN1
i3[5] => i3[5]~10.IN1
i3[6] => i3[6]~9.IN1
i3[7] => i3[7]~8.IN1
i3[8] => i3[8]~7.IN1
i3[9] => i3[9]~6.IN1
i3[10] => i3[10]~5.IN1
i3[11] => i3[11]~4.IN1
i3[12] => i3[12]~3.IN1
i3[13] => i3[13]~2.IN1
i3[14] => i3[14]~1.IN1
i3[15] => i3[15]~0.IN1
i4 => i4~0.IN4
i5 => i5~0.IN4
o1 <= cf_fft_1024_8_6:s2.port6
o2[0] <= cf_fft_1024_8_6:s2.port7
o2[1] <= cf_fft_1024_8_6:s2.port7
o2[2] <= cf_fft_1024_8_6:s2.port7
o2[3] <= cf_fft_1024_8_6:s2.port7
o2[4] <= cf_fft_1024_8_6:s2.port7
o2[5] <= cf_fft_1024_8_6:s2.port7
o2[6] <= cf_fft_1024_8_6:s2.port7
o2[7] <= cf_fft_1024_8_6:s2.port7
o2[8] <= cf_fft_1024_8_6:s2.port7
o2[9] <= cf_fft_1024_8_6:s2.port7
o2[10] <= cf_fft_1024_8_6:s2.port7
o2[11] <= cf_fft_1024_8_6:s2.port7
o2[12] <= cf_fft_1024_8_6:s2.port7
o2[13] <= cf_fft_1024_8_6:s2.port7
o2[14] <= cf_fft_1024_8_6:s2.port7
o2[15] <= cf_fft_1024_8_6:s2.port7
o3[0] <= cf_fft_1024_8_6:s2.port8
o3[1] <= cf_fft_1024_8_6:s2.port8
o3[2] <= cf_fft_1024_8_6:s2.port8
o3[3] <= cf_fft_1024_8_6:s2.port8
o3[4] <= cf_fft_1024_8_6:s2.port8
o3[5] <= cf_fft_1024_8_6:s2.port8
o3[6] <= cf_fft_1024_8_6:s2.port8
o3[7] <= cf_fft_1024_8_6:s2.port8
o3[8] <= cf_fft_1024_8_6:s2.port8
o3[9] <= cf_fft_1024_8_6:s2.port8
o3[10] <= cf_fft_1024_8_6:s2.port8
o3[11] <= cf_fft_1024_8_6:s2.port8
o3[12] <= cf_fft_1024_8_6:s2.port8
o3[13] <= cf_fft_1024_8_6:s2.port8
o3[14] <= cf_fft_1024_8_6:s2.port8
o3[15] <= cf_fft_1024_8_6:s2.port8


|fft|cf_fft_1024_8:fft2|cf_fft_1024_8_1:s1|cf_fft_1024_8_23:s1
clock_c => clock_c~0.IN5
i1 => i1~0.IN1
i2[0] => i2[0]~15.IN1
i2[1] => i2[1]~14.IN1
i2[2] => i2[2]~13.IN1
i2[3] => i2[3]~12.IN1
i2[4] => i2[4]~11.IN1
i2[5] => i2[5]~10.IN1
i2[6] => i2[6]~9.IN1
i2[7] => i2[7]~8.IN1
i2[8] => i2[8]~7.IN1
i2[9] => i2[9]~6.IN1
i2[10] => i2[10]~5.IN1
i2[11] => i2[11]~4.IN1
i2[12] => i2[12]~3.IN1
i2[13] => i2[13]~2.IN1
i2[14] => i2[14]~1.IN1
i2[15] => i2[15]~0.IN1
i3[0] => i3[0]~15.IN1
i3[1] => i3[1]~14.IN1
i3[2] => i3[2]~13.IN1
i3[3] => i3[3]~12.IN1
i3[4] => i3[4]~11.IN1
i3[5] => i3[5]~10.IN1
i3[6] => i3[6]~9.IN1
i3[7] => i3[7]~8.IN1
i3[8] => i3[8]~7.IN1
i3[9] => i3[9]~6.IN1
i3[10] => i3[10]~5.IN1
i3[11] => i3[11]~4.IN1
i3[12] => i3[12]~3.IN1
i3[13] => i3[13]~2.IN1
i3[14] => i3[14]~1.IN1
i3[15] => i3[15]~0.IN1
i4 => i4~0.IN5
i5 => i5~0.IN5
o1 <= s28_1.DB_MAX_OUTPUT_PORT_TYPE
o2[0] <= n23~15.DB_MAX_OUTPUT_PORT_TYPE
o2[1] <= n23~14.DB_MAX_OUTPUT_PORT_TYPE
o2[2] <= n23~13.DB_MAX_OUTPUT_PORT_TYPE
o2[3] <= n23~12.DB_MAX_OUTPUT_PORT_TYPE
o2[4] <= n23~11.DB_MAX_OUTPUT_PORT_TYPE
o2[5] <= n23~10.DB_MAX_OUTPUT_PORT_TYPE
o2[6] <= n23~9.DB_MAX_OUTPUT_PORT_TYPE
o2[7] <= n23~8.DB_MAX_OUTPUT_PORT_TYPE
o2[8] <= n23~7.DB_MAX_OUTPUT_PORT_TYPE
o2[9] <= n23~6.DB_MAX_OUTPUT_PORT_TYPE
o2[10] <= n23~5.DB_MAX_OUTPUT_PORT_TYPE
o2[11] <= n23~4.DB_MAX_OUTPUT_PORT_TYPE
o2[12] <= n23~3.DB_MAX_OUTPUT_PORT_TYPE
o2[13] <= n23~2.DB_MAX_OUTPUT_PORT_TYPE
o2[14] <= n23~1.DB_MAX_OUTPUT_PORT_TYPE
o2[15] <= n23~0.DB_MAX_OUTPUT_PORT_TYPE
o3[0] <= n24~15.DB_MAX_OUTPUT_PORT_TYPE
o3[1] <= n24~14.DB_MAX_OUTPUT_PORT_TYPE
o3[2] <= n24~13.DB_MAX_OUTPUT_PORT_TYPE
o3[3] <= n24~12.DB_MAX_OUTPUT_PORT_TYPE
o3[4] <= n24~11.DB_MAX_OUTPUT_PORT_TYPE
o3[5] <= n24~10.DB_MAX_OUTPUT_PORT_TYPE
o3[6] <= n24~9.DB_MAX_OUTPUT_PORT_TYPE
o3[7] <= n24~8.DB_MAX_OUTPUT_PORT_TYPE
o3[8] <= n24~7.DB_MAX_OUTPUT_PORT_TYPE
o3[9] <= n24~6.DB_MAX_OUTPUT_PORT_TYPE
o3[10] <= n24~5.DB_MAX_OUTPUT_PORT_TYPE
o3[11] <= n24~4.DB_MAX_OUTPUT_PORT_TYPE
o3[12] <= n24~3.DB_MAX_OUTPUT_PORT_TYPE
o3[13] <= n24~2.DB_MAX_OUTPUT_PORT_TYPE
o3[14] <= n24~1.DB_MAX_OUTPUT_PORT_TYPE
o3[15] <= n24~0.DB_MAX_OUTPUT_PORT_TYPE


|fft|cf_fft_1024_8:fft2|cf_fft_1024_8_1:s1|cf_fft_1024_8_23:s1|cf_fft_1024_8_39:s25
clock_c => n1[15].CLK
clock_c => n1[14].CLK
clock_c => n1[13].CLK
clock_c => n1[12].CLK
clock_c => n1[11].CLK
clock_c => n1[10].CLK
clock_c => n1[9].CLK
clock_c => n1[8].CLK
clock_c => n1[7].CLK
clock_c => n1[6].CLK
clock_c => n1[5].CLK
clock_c => n1[4].CLK
clock_c => n1[3].CLK
clock_c => n1[2].CLK
clock_c => n1[1].CLK
clock_c => n1[0].CLK
clock_c => n4[15].CLK
clock_c => n4[14].CLK
clock_c => n4[13].CLK
clock_c => n4[12].CLK
clock_c => n4[11].CLK
clock_c => n4[10].CLK
clock_c => n4[9].CLK
clock_c => n4[8].CLK
clock_c => n4[7].CLK
clock_c => n4[6].CLK
clock_c => n4[5].CLK
clock_c => n4[4].CLK
clock_c => n4[3].CLK
clock_c => n4[2].CLK
clock_c => n4[1].CLK
clock_c => n4[0].CLK
clock_c => n7[7].CLK
clock_c => n7[6].CLK
clock_c => n7[5].CLK
clock_c => n7[4].CLK
clock_c => n7[3].CLK
clock_c => n7[2].CLK
clock_c => n7[1].CLK
clock_c => n7[0].CLK
clock_c => n8[7].CLK
clock_c => n8[6].CLK
clock_c => n8[5].CLK
clock_c => n8[4].CLK
clock_c => n8[3].CLK
clock_c => n8[2].CLK
clock_c => n8[1].CLK
clock_c => n8[0].CLK
clock_c => n9[7].CLK
clock_c => n9[6].CLK
clock_c => n9[5].CLK
clock_c => n9[4].CLK
clock_c => n9[3].CLK
clock_c => n9[2].CLK
clock_c => n9[1].CLK
clock_c => n9[0].CLK
clock_c => n10[7].CLK
clock_c => n10[6].CLK
clock_c => n10[5].CLK
clock_c => n10[4].CLK
clock_c => n10[3].CLK
clock_c => n10[2].CLK
clock_c => n10[1].CLK
clock_c => n10[0].CLK
clock_c => n11[15].CLK
clock_c => n11[14].CLK
clock_c => n11[13].CLK
clock_c => n11[12].CLK
clock_c => n11[11].CLK
clock_c => n11[10].CLK
clock_c => n11[9].CLK
clock_c => n11[8].CLK
clock_c => n11[7].CLK
clock_c => n11[6].CLK
clock_c => n11[5].CLK
clock_c => n11[4].CLK
clock_c => n11[3].CLK
clock_c => n11[2].CLK
clock_c => n11[1].CLK
clock_c => n11[0].CLK
clock_c => n16[7].CLK
clock_c => n16[6].CLK
clock_c => n16[5].CLK
clock_c => n16[4].CLK
clock_c => n16[3].CLK
clock_c => n16[2].CLK
clock_c => n16[1].CLK
clock_c => n16[0].CLK
clock_c => n19[7].CLK
clock_c => n19[6].CLK
clock_c => n19[5].CLK
clock_c => n19[4].CLK
clock_c => n19[3].CLK
clock_c => n19[2].CLK
clock_c => n19[1].CLK
clock_c => n19[0].CLK
clock_c => n21[7].CLK
clock_c => n21[6].CLK
clock_c => n21[5].CLK
clock_c => n21[4].CLK
clock_c => n21[3].CLK
clock_c => n21[2].CLK
clock_c => n21[1].CLK
clock_c => n21[0].CLK
clock_c => n24[7].CLK
clock_c => n24[6].CLK
clock_c => n24[5].CLK
clock_c => n24[4].CLK
clock_c => n24[3].CLK
clock_c => n24[2].CLK
clock_c => n24[1].CLK
clock_c => n24[0].CLK
clock_c => n27[7].CLK
clock_c => n27[6].CLK
clock_c => n27[5].CLK
clock_c => n27[4].CLK
clock_c => n27[3].CLK
clock_c => n27[2].CLK
clock_c => n27[1].CLK
clock_c => n27[0].CLK
clock_c => n29[7].CLK
clock_c => n29[6].CLK
clock_c => n29[5].CLK
clock_c => n29[4].CLK
clock_c => n29[3].CLK
clock_c => n29[2].CLK
clock_c => n29[1].CLK
clock_c => n29[0].CLK
clock_c => n33[15].CLK
clock_c => n33[14].CLK
clock_c => n33[13].CLK
clock_c => n33[12].CLK
clock_c => n33[11].CLK
clock_c => n33[10].CLK
clock_c => n33[9].CLK
clock_c => n33[8].CLK
clock_c => n33[7].CLK
clock_c => n33[6].CLK
clock_c => n33[5].CLK
clock_c => n33[4].CLK
clock_c => n33[3].CLK
clock_c => n33[2].CLK
clock_c => n33[1].CLK
clock_c => n33[0].CLK
clock_c => n37[15].CLK
clock_c => n37[14].CLK
clock_c => n37[13].CLK
clock_c => n37[12].CLK
clock_c => n37[11].CLK
clock_c => n37[10].CLK
clock_c => n37[9].CLK
clock_c => n37[8].CLK
clock_c => n37[7].CLK
clock_c => n37[6].CLK
clock_c => n37[5].CLK
clock_c => n37[4].CLK
clock_c => n37[3].CLK
clock_c => n37[2].CLK
clock_c => n37[1].CLK
clock_c => n37[0].CLK
i1[0] => n1~15.DATAB
i1[1] => n1~14.DATAB
i1[2] => n1~13.DATAB
i1[3] => n1~12.DATAB
i1[4] => n1~11.DATAB
i1[5] => n1~10.DATAB
i1[6] => n1~9.DATAB
i1[7] => n1~8.DATAB
i1[8] => n1~7.DATAB
i1[9] => n1~6.DATAB
i1[10] => n1~5.DATAB
i1[11] => n1~4.DATAB
i1[12] => n1~3.DATAB
i1[13] => n1~2.DATAB
i1[14] => n1~1.DATAB
i1[15] => n1~0.DATAB
i2[0] => n4~15.DATAB
i2[1] => n4~14.DATAB
i2[2] => n4~13.DATAB
i2[3] => n4~12.DATAB
i2[4] => n4~11.DATAB
i2[5] => n4~10.DATAB
i2[6] => n4~9.DATAB
i2[7] => n4~8.DATAB