fft.v.bak

利用FPGA的IP核来实现fft的设计

`timescale 1ns/10ps
module fft(
           clock_c,
           enable_i,
           reset_i,
           sync_i,
           data_0_i,
           data_1_i,
//----------------------------------------
           sync_o,
           data_0_o,
           data_1_o
          );
input  clock_c;
input  enable_i;
input  reset_i;
input  sync_i;
input  [15:0] data_0_i;
input  [15:0] data_1_i;
output sync_o;
output [15:0] data_0_o;
output [15:0] data_1_o;

cf_fft_1024_8 fft2(
                   .clock_c(clock_c),
                   .enable_i(enable_i),
                   .reset_i(reset_i),
                   .sync_i(sync_i),
                   .data_0_i(data_0_i),
                   .data_1_i(data_1_i),
//----------------------------------------
                   .sync_o(sync_o),
                   .data_0_o(data_0_o),
                   .data_1_o(data_1_o)
                  );

endmodule