sh3.inc

WINDOWS CE BSP用于SBC2440开发板

; MCR: Individual memory control register (RAS/CAS timing and burst control for
; DRAM, SRAM and PSRAM, address multiplexing, and refresh control.

BCN_MCR_TPC:		.equ	0xc000	; RAS precharge time mask
BCN_MCR_TPC_1:		.equ	0x0000	; 1 cycle
BCN_MCR_TPC_2:		.equ	0x4000	; 2 cycles
BCN_MCR_TPC_3:		.equ	0x8000	; 3 cycles
BCN_MCR_TPC_4:		.equ	0xc000	; 4 cycles

BCN_MCR_RCD:		.equ	0x3000	; RAS-CAS delay mask
BCN_MCR_RCD_1:		.equ	0x0000	; 1 cycle
BCN_MCR_RCD_2:		.equ	0x1000	; 2 cycles
BCN_MCR_RCD_3:		.equ	0x2000	; 3 cycles
BCN_MCR_RCD_4:		.equ	0x3000	; 4 cycles

BCN_MCR_TRWL:		.equ	0x0c00	; Write-precharge delay
BCN_MCR_TRWL_1:		.equ	0x0000	; 1 cycle
BCN_MCR_TRWL_2:		.equ	0x0400	; 2 cycles
BCN_MCR_TRWL_3:		.equ	0x0800	; 3 cycles

BCN_MCR_TRAS:		.equ	0x0300	; RAS precharge time mask
BCN_MCR_TRAS_2:		.equ	0x0000	; 2 cycles
BCN_MCR_TRAS_3:		.equ	0x0100	; 3 cycles
BCN_MCR_TRAS_4:		.equ	0x0200	; 4 cycles
BCN_MCR_TRAS_5:		.equ	0x0300	; 5 cycles

BCN_MCR_BE:		.equ	0x0040	; Burst enable
BCN_MCR_SZ:		.equ	0x0020	; Memory data size, 0 => 16, 1 => 32

BCN_MCR_AMX:		.equ	0x0018	; Address multiplex mask
BCN_MCR_AMX_9:		.equ	0x0000	; Row addr begins with A9
BCN_MCR_AMX_10:		.equ	0x0008	; Row addr begins with A10
BCN_MCR_AMX_11:		.equ	0x0010	; Row addr begins with A11
BCN_MCR_AMX_12:		.equ	0x0018	; Row addr begins with A12 (9 for SDRAM)

BCN_MCR_RFSH:		.equ	0x0004	; Refresh enable
BCN_MCR_RMODE:		.equ	0x0002	; Refresh mode, 0 => ordinary, 1 => self
BCN_MCR_HSMODE:		.equ	0x0001	; High speed mode

; Values that will be written to many of the following registers must be ORed
; with their corresponding *_*_COOKIE value before writing the register.
; Otherwise, the hardware will reject (ignore) the write.

; RTCSR: Refresh timer control/status register (refresh cycle, interrupt enable,
; and the interrupt's cycle).

BCN_RTCSR_COOKIE:	.equ	0xa500	; OR with new value before writing
BCN_RTCSR_CMF:		.equ	0x0080	; Predicate, RTCNT == RTCOR
BCN_RTCSR_CMIE:		.equ	0x0040	; Enable an interrupt via CMF

BCN_RTCSR_CKS:		.equ	0x0038	; Clock select mask
BCN_RTCSR_CKS_DISABLE:	.equ	0x0000	; Disable clock input
BCN_RTCSR_CKS_4:	.equ	0x0008	; CKIO/4
BCN_RTCSR_CKS_16:	.equ	0x0010	; CKIO/16
BCN_RTCSR_CKS_64:	.equ	0x0018	; CKIO/64
BCN_RTCSR_CKS_256:	.equ	0x0020	; CKIO/256
BCN_RTCSR_CKS_1024:	.equ	0x0028	; CKIO/1024
BCN_RTCSR_CKS_2048:	.equ	0x0030	; CKIO/2048
BCN_RTCSR_CKS_4096:	.equ	0x0038	; CKIO/4096

BCN_RTCSR_OVF:		.equ	0x0004	; RFCR has exceeded count limit in LMTS
BCN_RTCSR_OVIE:		.equ	0x0002	; Enable an interrupt via OVF
BCN_RTCSR_LMTS:		.equ	0x0001	; Count limit: 0 => 1024, 1 => 512

; RTCNT: Refresh timer counter.

BCN_RTCNT_COOKIE:	.equ	0xa500	; OR with new value before writing
BCN_RTCNT_COUNT:	.equ	0x00ff	; Refresh timer counter mask

; RTCOR: Refresh time constant register.

BCN_RTCOR_COOKIE:	.equ	0xa500	; OR with new value before writing
BCN_RTCOR_COUNT:	.equ	0x00ff	; Refresh time constant mask

; RFCR: Refresh count register.

BCN_RFCR_COOKIE:	.equ	0xa400	; OR with new value before writing
BCN_RFCR_COUNT:		.equ	0x03ff	; Refresh count mask

;
; Clock pulse generator registers.
;

CPG_FRQCR:	.equ	0xffffff80	; Frequency control register
CPG_WTCNT:	.equ	0xffffff84	; Watchdog timer counter
CPG_WTCSR:	.equ	0xffffff86	; Watchdog timer control/status register

; Frequency control register.

CPG_FRQCR_CKOEN:	.equ	0x0100	; Clock enable
CPG_FRQCR_PLLEN:	.equ	0x0080	; PLL circuit 1 enable
CPG_FRQCR_PSTBY:	.equ	0x0040	; PLL 1 standby

CPG_FRQCR_STC:		.equ	0x0030	; PLL 1 frequency multiplication rate
CPG_FRQCR_STC_1:	.equ	0x0000	; x1
CPG_FRQCR_STC_2:	.equ	0x0010	; x2
CPG_FRQCR_STC_4:	.equ	0x0020	; x4

CPG_FRQCR_IFC:		.equ	0x000c	; Internal clock freq divider 1 rate
CPG_FRQCR_IFC_1:	.equ	0x0000	; /1
CPG_FRQCR_IFC_2:	.equ	0x0004	; /2
CPG_FRQCR_IFC_4:	.equ	0x0008	; /4

CPG_FRQCR_PFC:		.equ	0x0003	; Peripheral clock freq divider 2 rate
CPG_FRQCR_PFC_1:	.equ	0x0000	; /1
CPG_FRQCR_PFC_2:	.equ	0x0001	; /2
CPG_FRQCR_PFC_4:	.equ	0x0002	; /4

; Watchdog timer counter.

CPG_WTCNT_COOKIE:	.equ	0x5a00	; OR with new value before writing
CPG_WTCNT_COUNT:	.equ	0x00ff	; Watchdog timer counter mask

; Watchdog timer control/status register.

CPG_WTCSR_COOKIE:	.equ	0xa500	; OR with new value before writing
CPG_WTCSR_TME:		.equ	0x0080	; Timer enable
CPG_WTCSR_WT:		.equ	0x0040	; Timer mode select, 1 <=> watchdog
CPG_WTCSR_RSTS:		.equ	0x0020	; Reset select
CPG_WTCSR_WOVF:		.equ	0x0010	; Watchdog timer overflow
CPG_WTCSR_IOVF:		.equ	0x0008	; Interval timer overflow

CPG_WTCSR_CKS:		.equ	0x0007	; Clock select, periph clock div ratio
CPG_WTCSR_CKS_1:	.equ	0x0000	; /1
CPG_WTCSR_CKS_4:	.equ	0x0001	; /4
CPG_WTCSR_CKS_16:	.equ	0x0002	; /16
CPG_WTCSR_CKS_32:	.equ	0x0003	; /32
CPG_WTCSR_CKS_64:	.equ	0x0004	; /64
CPG_WTCSR_CKS_256:	.equ	0x0005	; /256
CPG_WTCSR_CKS_1024:	.equ	0x0006	; /1024
CPG_WTCSR_CKS_4096:	.equ	0x0007	; /4096

;
; Cache controller registers (though most aren't).
;

CCN_TRA:	.equ	0xffffffd0	; TRAPA exception register
CCN_EXPEVT:	.equ	0xffffffd4	; Exception event register
CCN_INTEVT:	.equ	0xffffffd8	; Interrupt event register
CCN_CCR:	.equ	0xffffffec	; Cache control register

; Cache control register.

CCN_CCR_RA:	.equ	0x00000020	; RAM mode (1/2 of cache acts as RAM)
CCN_CCR_CF:	.equ	0x00000008	; Cache flush
CCN_CCR_CB:	.equ	0x00000004	; P1 Mode: 0 => write-thru, 1 => write-back
CCN_CCR_WT:	.equ	0x00000002	; Mode: 0 => write-back, 1 => write-thru
CCN_CCR_CE:	.equ	0x00000001	; Cache enable



;* SH3 Timer unit registers

TMU_BASE: .equ  h'fffffe90
TMU_OCR: .equ   h'00    ; timer output control (8 bit)
TMU_STR: .equ   h'02    ; timer start register (8 bit)

TMU_START0: .equ h'01
TMU_START1: .equ h'02
TMU_START2: .equ h'04

TMU_COR0: .equ  h'04    ; timer constant 0 (32 bit)
TMU_CNT0: .equ  h'08    ; timer count 0 (32 bit)
TMU_CR0: .equ   h'0c    ; timer control 0 (16 bit)

TMU_COR1: .equ  h'10    ; timer constant 1 (32 bit)
TMU_CNT1: .equ  h'14    ; timer count 1 (32 bit)
TMU_CR1: .equ   h'18    ; timer control 1 (16 bit)

TMU_COR2: .equ  h'1c    ; timer constant 2 (32 bit)
TMU_CNT2: .equ  h'20    ; timer count 2 (32 bit)
TMU_CR2: .equ   h'24    ; timer control 2 (16 bit)
TMU_CPR2: .equ  h'28    ; input capture 2 (32 bit)

TMUCR_UNF: .equ h'100   ; counter underflowed
TMUCR_UNIE: .equ h'20   ; underflow interrupt enable

TMUCR_RISE: .equ h'00   ; count on rising edge of clock
TMUCR_FALL: .equ h'08   ; count on falling edge of clock
TMUCR_BOTH: .equ h'10   ; count on both edges of clock

TMUCR_D4:   .equ h'00   ; PERIPHERAL clock / 4
TMUCR_D16:  .equ h'01   ; PERIPHERAL clock / 16
TMUCR_D64:  .equ h'02   ; PERIPHERAL clock / 64
TMUCR_D256: .equ h'03   ; PERIPHERAL clock / 256
TMUCR_RTC:  .equ h'04   ; real time clock output (16 kHz)
TMUCR_EXT:  .equ h'05   ; external clock input

;RTC
RTC_BASE        .equ    h'FFFFFEC0
RTC_64CNT       .equ    h'0000          ;8
RTC_SECCNT      .equ    h'0002          ;8
RTC_MINCNT      .equ    h'0004          ;8
RTC_HRCNT       .equ    h'0006          ;8
RTC_WKCNT       .equ    h'0008          ;8
RTC_DAYCNT      .equ    h'000a          ;8
RTC_MONCNT      .equ    h'000c          ;8
RTC_YRCNT       .equ    h'000e          ;8
RTC_SECAR       .equ    h'0010          ;8
RTC_MINAR       .equ    h'0012          ;8
RTC_HRAR        .equ    h'0014          ;8
RTC_WKAR        .equ    h'0016          ;8
RTC_DAYAR       .equ    h'0018          ;8
RTC_MONAR       .equ    h'001a          ;8
RTC_CR1         .equ    h'001c          ;8
RTC_CR2         .equ    h'001e          ;8

; Power control registers
STBCR       .equ   0xFFFFFF82    ;   Standby control register