sh3.inc

WINDOWS CE BSP用于SBC2440开发板

;++
;Copyright (c) 1999-2000 Microsoft Corporation.  All rights reserved.
;
; Module Name:
;
;    sh3.inc
;
; Abstract:
;
;    This module defines names for the SH-3's on-chip control and status
;    registers, and their fields.  It is directly based on the SH-3 Hardware
;    Reference Manual.
;
; Author:
;
;    David Neff (dneff) 5-Jul-1996
;
; Environment:
;
;    SH-3 privileged mode.
;
; Revision History:
;
;--

; SH-3 register definitions.  The prefix of each register name is derived from
; the module name in table A.1 of the SH-3 Hardware Reference Manual.

;
; Bus state controller registers.
;

BCN_BCR1:	.equ	0xffffff60	; Bus control register 1
BCN_BCR2:	.equ	0xffffff62	; Bus control register 2
BCN_WCR1:	.equ	0xffffff64	; Wait state control register 1
BCN_WCR2:	.equ	0xffffff66	; Wait state control register 2
BCN_MCR:	.equ	0xffffff68	; Individual memory control register
BCN_DCR:	.equ	0xffffff6a	; DRAM control register
BCN_PCR:	.equ	0xffffff6c	; PCMCIA control register
BCN_RTCSR:	.equ	0xffffff6e	; Refresh timer control/status register
BCN_RTCNT:	.equ	0xffffff70	; Refresh timer counter
BCN_RTCOR:	.equ	0xffffff72	; Refresh time constant register
BCN_RFCR:	.equ	0xffffff74	; Refresh count register

; BCR1: bus control register 1 fields (function and bus cycle status for each
; area).

BCN_BCR1_ENDIAN:	.equ	0x0800	; 1 <=> little endian

BCN_BCR1_A0BST:		.equ	0x0600	; Area 0 burst mask
BCN_BCR1_A0BST_N:	.equ	0x0000	; Area 0 ordinary memory
BCN_BCR1_A0BST_4:	.equ	0x0200	; Area 0 burst (4 consecutive accesses)
BCN_BCR1_A0BST_8:	.equ	0x0400	; Area 0 burst (8 consecutive accesses)
BCN_BCR1_A0BST_16:	.equ	0x0600	; Area 0 burst (16 consecutive accesses)

BCN_BCR1_A5BST:		.equ	0x0180	; Area 5 burst mask
BCN_BCR1_A5BST_N:	.equ	0x0000	; Area 5 ordinary memory
BCN_BCR1_A5BST_4:	.equ	0x0080	; Area 5 burst (4 consecutive accesses)
BCN_BCR1_A5BST_8:	.equ	0x0100	; Area 5 burst (8 consecutive accesses)
BCN_BCR1_A5BST_16:	.equ	0x0180	; Area 5 burst (16 consecutive accesses)

BCN_BCR1_A6BST:		.equ	0x0060	; Area 6 burst mask
BCN_BCR1_A6BST_N:	.equ	0x0000	; Area 6 ordinary memory
BCN_BCR1_A6BST_4:	.equ	0x0020	; Area 6 burst (4 consecutive accesses)
BCN_BCR1_A6BST_8:	.equ	0x0040	; Area 6 burst (8 consecutive accesses)
BCN_BCR1_A6BST_16:	.equ	0x0060	; Area 6 burst (16 consecutive accesses)

BCN_BCR1_DRAM:		.equ	0x001c	; Areas 2 & 3 mask
BCN_BCR1_DRAM_A2N3N:	.equ	0x0000	; Area 2 normal, Area 3 normal
BCN_BCR1_DRAM_A2N3P:	.equ	0x0004	; Area 2 normal, Area 3 PSRAM
BCN_BCR1_DRAM_A2N3S:	.equ	0x0008	; Area 2 normal, Area 3 SDRAM
BCN_BCR1_DRAM_A2S3S:	.equ	0x000c	; Area 2 SDRAM, Area 3 SDRAM
BCN_BCR1_DRAM_A2N3D:	.equ	0x0010	; Area 2 normal, Area 3 DRAM
BCN_BCR1_DRAM_A2D3D:	.equ	0x0014	; Area 2 DRAM, Area 3 DRAM

BCN_BCR1_A5PCM:		.equ	0x0002	; Area 5 is PCMCIA access
BCN_BCR1_A6PCM:		.equ	0x0001	; Area 6 is PCMCIA access

; BCR2: bus control register 2 fields (bus size width of each area).

BCN_BCR2_A6SZ:		.equ	0x3000	; Area 6 mask
BCN_BCR2_A6SZ_8:	.equ	0x1000	; Area 6 is  8-bit memory
BCN_BCR2_A6SZ_16:	.equ	0x2000	; Area 6 is 16-bit memory
BCN_BCR2_A6SZ_32:	.equ	0x3000	; Area 6 is 32-bit memory

BCN_BCR2_A5SZ:		.equ	0x0c00	; Area 5 mask
BCN_BCR2_A5SZ_8:	.equ	0x0400	; Area 5 is  8-bit memory
BCN_BCR2_A5SZ_16:	.equ	0x0800	; Area 5 is 16-bit memory
BCN_BCR2_A5SZ_32:	.equ	0x0c00	; Area 5 is 32-bit memory

BCN_BCR2_A4SZ:		.equ	0x0300	; Area 4 mask
BCN_BCR2_A4SZ_8:	.equ	0x0100	; Area 4 is  8-bit memory
BCN_BCR2_A4SZ_16:	.equ	0x0200	; Area 4 is 16-bit memory
BCN_BCR2_A4SZ_32:	.equ	0x0300	; Area 4 is 32-bit memory

BCN_BCR2_A3SZ:		.equ	0x00c0	; Area 3 mask
BCN_BCR2_A3SZ_8:	.equ	0x0040	; Area 3 is  8-bit memory
BCN_BCR2_A3SZ_16:	.equ	0x0080	; Area 3 is 16-bit memory
BCN_BCR2_A3SZ_32:	.equ	0x00c0	; Area 3 is 32-bit memory

BCN_BCR2_A2SZ:		.equ	0x0030	; Area 2 mask
BCN_BCR2_A2SZ_8:	.equ	0x0010	; Area 2 is  8-bit memory
BCN_BCR2_A2SZ_16:	.equ	0x0020	; Area 2 is 16-bit memory
BCN_BCR2_A2SZ_32:	.equ	0x0030	; Area 2 is 32-bit memory

BCN_BCR2_A1SZ:		.equ	0x000c	; Area 1 mask
BCN_BCR2_A1SZ_8:	.equ	0x0004	; Area 1 is  8-bit memory
BCN_BCR2_A1SZ_16:	.equ	0x0008	; Area 1 is 16-bit memory
BCN_BCR2_A1SZ_32:	.equ	0x000c	; Area 1 is 32-bit memory

BCN_BCR2_PORTEN:	.equ	0x0001	; Port enable

; WCR1: Wait (idle) state control register 1 fields.

BCN_WCR1_A6IW:		.equ	0x3000	; Area 6 mask
BCN_WCR1_A6IW_0:	.equ	0x0000	; Area 6 has 0 idle states
BCN_WCR1_A6IW_1:	.equ	0x1000	; Area 6 has 1 idle states
BCN_WCR1_A6IW_2:	.equ	0x2000	; Area 6 has 2 idle states
BCN_WCR1_A6IW_3:	.equ	0x3000	; Area 6 has 3 idle states

BCN_WCR1_A5IW:		.equ	0x0c00	; Area 5 mask
BCN_WCR1_A5IW_0:	.equ	0x0000	; Area 5 has 0 idle states
BCN_WCR1_A5IW_1:	.equ	0x0400	; Area 5 has 1 idle states
BCN_WCR1_A5IW_2:	.equ	0x0800	; Area 5 has 2 idle states
BCN_WCR1_A5IW_3:	.equ	0x0c00	; Area 5 has 3 idle states

BCN_WCR1_A4IW:		.equ	0x0300	; Area 4 mask
BCN_WCR1_A4IW_0:	.equ	0x0000	; Area 4 has 0 idle states
BCN_WCR1_A4IW_1:	.equ	0x0100	; Area 4 has 1 idle states
BCN_WCR1_A4IW_2:	.equ	0x0200	; Area 4 has 2 idle states
BCN_WCR1_A4IW_3:	.equ	0x0300	; Area 4 has 3 idle states

BCN_WCR1_A3IW:		.equ	0x00c0	; Area 3 mask
BCN_WCR1_A3IW_0:	.equ	0x0000	; Area 3 has 0 idle states
BCN_WCR1_A3IW_1:	.equ	0x0040	; Area 3 has 1 idle states
BCN_WCR1_A3IW_2:	.equ	0x0080	; Area 3 has 2 idle states
BCN_WCR1_A3IW_3:	.equ	0x00c0	; Area 3 has 3 idle states

BCN_WCR1_A2IW:		.equ	0x0030	; Area 2 mask
BCN_WCR1_A2IW_0:	.equ	0x0000	; Area 2 has 0 idle states
BCN_WCR1_A2IW_1:	.equ	0x0010	; Area 2 has 1 idle states
BCN_WCR1_A2IW_2:	.equ	0x0020	; Area 2 has 2 idle states
BCN_WCR1_A2IW_3:	.equ	0x0030	; Area 2 has 3 idle states

BCN_WCR1_A1IW:		.equ	0x000c	; Area 1 mask
BCN_WCR1_A1IW_0:	.equ	0x0000	; Area 1 has 0 idle states
BCN_WCR1_A1IW_1:	.equ	0x0004	; Area 1 has 1 idle states
BCN_WCR1_A1IW_2:	.equ	0x0008	; Area 1 has 2 idle states
BCN_WCR1_A1IW_3:	.equ	0x000c	; Area 1 has 3 idle states

BCN_WCR1_A0IW:		.equ	0x0003	; Area 0 mask
BCN_WCR1_A0IW_0:	.equ	0x0000	; Area 0 has 0 idle states
BCN_WCR1_A0IW_1:	.equ	0x0001	; Area 0 has 1 idle states
BCN_WCR1_A0IW_2:	.equ	0x0002	; Area 0 has 2 idle states
BCN_WCR1_A0IW_3:	.equ	0x0003	; Area 0 has 3 idle states

; WCR2: Wait state control register 2 fields.

BCN_WCR2_A6W:		.equ	0xe000	; Area 6 wait state mask
BCN_WCR2_A6W_0:		.equ	0x0000	; Area 6 has 0 wait states
BCN_WCR2_A6W_1:		.equ	0x2000	; Area 6 has 1 wait states
BCN_WCR2_A6W_2:		.equ	0x4000	; Area 6 has 2 wait states
BCN_WCR2_A6W_3:		.equ	0x6000	; Area 6 has 3 wait states
BCN_WCR2_A6W_4:		.equ	0x8000	; Area 6 has 4 wait states
BCN_WCR2_A6W_6:		.equ	0xa000	; Area 6 has 6 wait states
BCN_WCR2_A6W_8:		.equ	0xc000	; Area 6 has 8 wait states
BCN_WCR2_A6W_10:	.equ	0xe000	; Area 6 has 10 wait states

BCN_WCR2_A5W:		.equ	0x1c00	; Area 5 wait state mask
BCN_WCR2_A5W_0:		.equ	0x0000	; Area 5 has 0 wait states
BCN_WCR2_A5W_1:		.equ	0x0400	; Area 5 has 1 wait states
BCN_WCR2_A5W_2:		.equ	0x0800	; Area 5 has 2 wait states
BCN_WCR2_A5W_3:		.equ	0x0c00	; Area 5 has 3 wait states
BCN_WCR2_A5W_4:		.equ	0x1000	; Area 5 has 4 wait states
BCN_WCR2_A5W_6:		.equ	0x1400	; Area 5 has 6 wait states
BCN_WCR2_A5W_8:		.equ	0x1800	; Area 5 has 8 wait states
BCN_WCR2_A5W_10:	.equ	0x1c00	; Area 5 has 10 wait states

BCN_WCR2_A4W:		.equ	0x0380	; Area 4 wait state mask
BCN_WCR2_A4W_0:		.equ	0x0000	; Area 4 has 0 wait states
BCN_WCR2_A4W_1:		.equ	0x0080	; Area 4 has 1 wait states
BCN_WCR2_A4W_2:		.equ	0x0100	; Area 4 has 2 wait states
BCN_WCR2_A4W_3:		.equ	0x0180	; Area 4 has 3 wait states
BCN_WCR2_A4W_4:		.equ	0x0200	; Area 4 has 4 wait states
BCN_WCR2_A4W_6:		.equ	0x0280	; Area 4 has 6 wait states
BCN_WCR2_A4W_8:		.equ	0x0300	; Area 4 has 8 wait states
BCN_WCR2_A4W_10:	.equ	0x0380	; Area 4 has 10 wait states

BCN_WCR2_A3W:		.equ	0x0060	; Area 3 wait state mask
BCN_WCR2_A3W_0:		.equ	0x0000	; Area 3 has 0 wait states
BCN_WCR2_A3W_1:		.equ	0x0020	; Area 3 has 1 wait states
BCN_WCR2_A3W_2:		.equ	0x0040	; Area 3 has 2 wait states
BCN_WCR2_A3W_3:		.equ	0x0060	; Area 3 has 3 wait states

BCN_WCR2_A12W:		.equ	0x0018	; Areas 1, 2 wait state mask
BCN_WCR2_A12W_0:	.equ	0x0000	; Areas 1, 2 have 0 wait states
BCN_WCR2_A12W_1:	.equ	0x0008	; Areas 1, 2 have 1 wait states
BCN_WCR2_A12W_2:	.equ	0x0010	; Areas 1, 2 have 2 wait states
BCN_WCR2_A12W_3:	.equ	0x0018	; Areas 1, 2 have 3 wait states

BCN_WCR2_A0W:		.equ	0x0007	; Area 0 wait state mask
BCN_WCR2_A0W_0:		.equ	0x0000	; Area 0 has 0 wait states
BCN_WCR2_A0W_1:		.equ	0x0001	; Area 0 has 1 wait states
BCN_WCR2_A0W_2:		.equ	0x0002	; Area 0 has 2 wait states
BCN_WCR2_A0W_3:		.equ	0x0003	; Area 0 has 3 wait states
BCN_WCR2_A0W_4:		.equ	0x0004	; Area 0 has 4 wait states
BCN_WCR2_A0W_6:		.equ	0x0005	; Area 0 has 6 wait states
BCN_WCR2_A0W_8:		.equ	0x0006	; Area 0 has 8 wait states
BCN_WCR2_A0W_10:	.equ	0x0007	; Area 0 has 10 wait states