reg4101.h

WINDOWS CE BSP用于SBC2440开发板

#define AudioEndIntr     0x0008  /* Crossed the Audio data to a page boundary in the case of acting AudioIntr in DMA transfer */

// Level 2 KIU interrupt / mask
#define KeySenseIntr     0x0001  /* Detects Key input */
#define KeyDataRdyIntr   0x0002  /* Indicates to finish scanning a set of key data */
#define KeyDataLostIntr  0x0004  /* Lost scan data */
#define KeyIntr          0x0008  /* Crossed the Key data to a page boundary in DMA transfer */
#define KeyEndIntr       0x0010  /* Crossed the Key data to a page boundary in the case of acting KeyIntr in DMA transfer */

// Level 2 GIU interrupt / mask
#define CardLockIntr     0x0001   /* Sets Interrupt in the case of changing the port's level */
#define BattLockIntr     0x0200   /* Sets Interrupt in the case of changing the port's level */
#define LcdRstIntr       0x0004   /* Sets Interrupt in the case of changing the port's level */
#define LcdBrupIntr      0x0008   /* Sets Interrupt in the case of changing the port's level */
#define LcdBrdnIntr      0x0010   /* Sets Interrupt in the case of changing the port's level */
#define DebIntIntr       0x0020   /* Sets Interrupt in the case of changing the port's level */
#define SIOPowEnIntr     0x0040  /* Sets Interrupt in the case of changing the port's level */
#define IrdaPowEnIntr    0x0080  /* Sets Interrupt in the case of changing the port's level */
#define PadPowEnIntr     0x0100  /* Sets Interrupt in the case of changing the port's level */
#define LcdPwrIntr       0x0200  /* Sets Interrupt in the case of changing the port's level */
#define LcdDpwrIntr      0x0400  /* Sets Interrupt in the case of changing the port's level */
#define GPIO2            0x0800   /* reserved */
#define GPIO1            0x8000   /* reserved */
#define GIUmask          0x7000    /* If you use G/A Ver 1.0 , you must mask on bit12 - 14. */
#define DCDChg		 0x2000   /* Sets Interrupt in the case of changing the port's level */
// Level 2 SIU interrupt /mask
#define txIntr           0x0001  /* Crossed the send data to a page boundary in DMA transfer */
#define txEndIntr        0x0002  /* Crossed the send data to a page boundary in the case of acting txIntr in DMA transfer */
#define rxIntr           0x0004  /* Crossed the received data to a page boundary in DMA transfer */
#define rxEndIntr        0x0008  /* Crossed the received data to a page boundary in the case of acting rxIntr in DMA transfer */
#define rxGetCharIntr    0x0010  /* Informs to finish received character */
#define rxLostCharIntr   0x0020  /* Informs to lost a received character */
#define CTSchgIntr       0x0040  /* Changes CTS status */
#define DSRchgIntr       0x0080  /* Changes DSR status */
#define DCDchgIntr       0x0100  /* Changes DCD status */
#define FEIntr           0x0200  /* Detects flaming error */
#define BrkIntr          0x0400  /* Detects Break signal */

// SOFT interrupt
// #define SoftIntr         0x0001  /* INTB interrupt */

// NMI
#define NMIorINT         0x0001     /* BatIntr is NMI or INTB */

//
// Interrupt Clear Register & Bit  (W1C)
//

/* 
  Interrupt clear bits for each unit in G/A.
*/

// PMUINTREG
#define BatIntr_clr          0x0002     // PMUINTREG writing
#define PowerIntr_clr        0x0001     // PMUINTREG writing

// RTC Unit
#define RtcLongIntr_clr      0x0001     // RTCINTREG writing
#define AlarmIntr_clr        0x0002     // RTCINTREG writing (ElapseTimeIntr)

//PCMCIA controller
#define IsaIntr_clr_index     0x83      // PCMCIA controler's index register writing
#define IsaIntr_clr           0x0       // PCMCIA controler's DATA register writing

// PIU Unit
#define PIUIntr_clr          0x001f     // PIUINTREG writing

// ADU Unit
#define ADUIntr_clr          0x000f     // ADUINTRREG writing

// KIU Unit
#define KIUIntr_clr          0x001f     // KIUINTREG writing

// GIU Unit
#define GIUIntr_clr          0x1fff     // GIUINTSTREG writing

// SIU Unit
#define SIUIntr_clr          0x07ff    // SIUINTREG writing

// BCU Unit
#define WrberrIntr_clr       0x0001    //BCUERRENREG writing

// Software interrupt
#define SoftIntr_clr         0x0000    // SOFTINTREG(0xab00009a) writing

// args for InitGA()
#define	COLDBOOT	0
#define	WARMBOOT	1


#define	INTRGRP_TCH	(PadIntr | PadEndIntr | PadDataRdyIntr | PadDataLostIntr)
#define	INTRGRP_TCH_CHG	(PadChgIntr)
#define	INTRGRP_KEY	(KeySenseIntr | KeyDataRdyIntr | KeyDataLostIntr | KeyIntr | KeyEndIntr)
//#define	INTRGRP_SERIAL	(txIntr | txEndIntr | rxIntr | rxEndIntr | rxLostCharIntr| \
//			 CTSchgIntr | DSRchgIntr | DCDchgIntr | FEIntr | BrkIntr)
// For Debug 96.6.17
#define	INTRGRP_SERIAL	(txIntr | txEndIntr | rxIntr | rxEndIntr | rxLostCharIntr| \
			 CTSchgIntr | DSRchgIntr | FEIntr | BrkIntr)
#define	INTRGRP_AUDIO	(AudioIDLEIntr | AudIntr | AudioEndIntr)
#define INTRGRP_GPIO    (DCDChg | BattLockIntr)
#define INTRGRP_POW     (PowerIntr  | BatIntr)



#define	SAVE_ICU_REGS

// CPU registers
#define	REGCPU_AT		0x00
#define	REGCPU_V0		0x04
#define	REGCPU_V1		0x08
#define	REGCPU_A0		0x0C
#define	REGCPU_A1		0x10
#define	REGCPU_A2		0x14
#define	REGCPU_A3		0x18
#define	REGCPU_T0		0x1C
#define	REGCPU_T1		0x20
#define	REGCPU_T2		0x24
#define	REGCPU_T3		0x28
#define	REGCPU_T4		0x2C
#define	REGCPU_T5		0x30
#define	REGCPU_T6		0x34
#define	REGCPU_T7		0x38
#define	REGCPU_S0		0x3C
#define	REGCPU_S1		0x40
#define	REGCPU_S2		0x44
#define	REGCPU_S3		0x48
#define	REGCPU_S4		0x4C
#define	REGCPU_S5		0x50
#define	REGCPU_S6		0x54
#define	REGCPU_S7		0x58
#define	REGCPU_T8		0x5C
#define	REGCPU_T9		0x60
#define	REGCPU_K0		0x64
#define	REGCPU_K1		0x68
#define	REGCPU_GP		0x6C
#define	REGCPU_SP		0x70
#define	REGCPU_S8		0x74
#define	REGCPU_RA		0x78

// CP0 registers
#define	REGCP0_INDEX		0x80
#define	REGCP0_RANDOM		0x84
#define	REGCP0_ENTRYLO0		0x88
#define	REGCP0_ENTRYLO1		0x8C
#define	REGCP0_CONTEXT		0x90
#define	REGCP0_PAGEMASK		0x94
#define	REGCP0_WIRED		0x98
#define	REGCP0_COUNT		0x9C
#define	REGCP0_ENTRYHI		0xA0
#define	REGCP0_COMPARE		0xA4
#define	REGCP0_PSR		0xA8
#define	REGCP0_CAUSE		0xAC
#define	REGCP0_EPC		0xB0
#define	REGCP0_CONFIG		0xB4
#define	REGCP0_LLADDR		0xB8
#define	REGCP0_WATCHLO		0xBC
#define	REGCP0_XCONTEXT		0xC0
#define	REGCP0_PERR		0xC4
#define	REGCP0_TAGLO		0xC8
#define	REGCP0_TAGHI		0xCC
#define	REGCP0_ERROREPC		0xD0

#ifdef SAVE_ICU_REGS
#define	REGGA_MSYSINTREG	0x100
#define	REGGA_MPIUINTREG	0x102
#define	REGGA_MADUINTREG	0x104
#define	REGGA_MKIUINTREG	0x106
#define	REGGA_MGIUINTREG	0x108
#define	REGGA_MSIUINTREG	0x10A
#endif


#define BUS_SPEED_VALUE		0x2321			//Default bus speed for R4101/Odo