mpc821.h

WINDOWS CE BSP用于SBC2440开发板

    volatile unsigned long clkrk_rsrk;
    volatile unsigned long clkrk_RESERVED1[29];

/* UNUSED REGIONS */
    volatile unsigned long UNUSED1[0x100];
    volatile unsigned long UNUSED2[0x10];

/* LCD */
	volatile unsigned long	lcd_lccr;	/* configuration Reg */
	volatile unsigned long	lcd_lchcr;	/* Horizontal ctl Reg */
	volatile unsigned long	lcd_lcvcr;	/* Vertical ctl Reg */
	unsigned char	RESERVED67[4];
	volatile unsigned long	lcd_lcfaa;	/* Frame buffer A Address */
	volatile unsigned long	lcd_lcfba;	/* Frame buffer B Address */
	volatile unsigned char	RESERVED9a[0x3];/* Reserved area */
	volatile unsigned char	lcd_lcsr;	/* Status Reg */
	volatile unsigned char	RESERVED9b[0x4];/* Reserved area */
/* I2C */
	unsigned char	RESERVED59[3];
	volatile unsigned char	i2c_i2mod;	/* i2c mode */
	unsigned char	RESERVED60[3];
	volatile unsigned char	i2c_i2add;	/* i2c address */
	unsigned char	RESERVED61[3];
	volatile unsigned char	i2c_i2brg;	/* i2c brg */
	unsigned char	RESERVED62[3];
	volatile unsigned char	i2c_i2com;	/* i2c command */
	unsigned char	RESERVED63[3];
	volatile unsigned char	i2c_i2cer;	/* i2c event */
	volatile unsigned char	RESERVED10a[0x3];/* Reserved area */
	volatile unsigned char	i2c_i2cmr;	/* i2c mask */
	volatile unsigned char	RESERVED10b[0x88];/* Reserved area */
/* DMA */
	volatile unsigned char	RESERVED11[0x4];/* Reserved area */
	volatile unsigned long	dma_sdar;	/* SDMA address reg */
	volatile unsigned char	RESERVED13[0x3];/* Reserved area */
	volatile unsigned char	dma_sdsr;	/* SDMA status reg */
	volatile unsigned char	RESERVED14[0x3];/* Reserved area */
	volatile unsigned char	dma_sdmr;	/* SDMA mask reg */
	volatile unsigned char	RESERVED15[0x3];/* Reserved area */
	volatile unsigned char	dma_idsr1;	/* IDMA1 status reg */
	volatile unsigned char	RESERVED16[0x3];/* Reserved area */
	volatile unsigned char	dma_idmr1;	/* IDMA1 mask reg */
	volatile unsigned char	RESERVED17[0x3];/* Reserved area */
	volatile unsigned char	dma_idsr2;	/* IDMA2 status reg */
	volatile unsigned char	RESERVED18a[0x3];/* Reserved area */
	volatile unsigned char	dma_idmr2;	/* IDMA2 mask reg */
	volatile unsigned char	RESERVED18b[0x10];/* Reserved area */
/* CPM Interrupt Controller */
	volatile unsigned char	RESERVED19a[0x2];/* Reserved area */
	volatile unsigned short	cpmi_civr;	/* CP interrupt vector reg */
	volatile unsigned char	RESERVED19b[0xc];/* Reserved area */
	volatile unsigned long	cpmi_cicr;	/* CP interrupt configuration reg */
	volatile unsigned long	cpmi_cipr;	/* CP interrupt pending reg */
	volatile unsigned long	cpmi_cimr;	/* CP interrupt mask reg */
	volatile unsigned long	cpmi_cisr;	/* CP interrupt in-service reg */
/* I/O port */
	volatile unsigned short	pio_papar;	/* port A pin assignment reg */
	volatile unsigned short	pio_padir;	/* port A data direction reg */
	volatile unsigned short	pio_padat;	/* port A data register */
	volatile unsigned short	pio_paodr;	/* port A open drain reg */
	volatile unsigned char	RESERVED20[0x8];	/* Reserved area */
	volatile unsigned short	pio_pcpar;	/* port C pin assignment reg */
	volatile unsigned short	pio_pcdir;	/* port C data direction reg */
	volatile unsigned short	pio_pcdat;	/* port C data register */
	volatile unsigned short	pio_pcso;	/* port C special options */
	unsigned char	RESERVED64a[2];
	volatile unsigned short	pio_pcint;	/* port C interrupt cntrl reg */
	unsigned char	RESERVED64b[4];
	volatile unsigned short	pio_pdpar;	/* port D pin assignment reg */
	volatile unsigned short	pio_pddir;	/* port D Data Direction reg */
	volatile unsigned short	pio_pddat;	/* port D data reg */
	unsigned char	RESERVED65[2];
	volatile unsigned char	RESERVED21[0x8];	/* Reserved area */
/* CPM Timer */
	volatile unsigned char	RESERVED22a[0x2];	/* Reserved area */
	volatile unsigned short	timer_tgcr;	/* timer global configuration  reg */
	volatile unsigned char	RESERVED22b[0xc];	/* Reserved area */
	volatile unsigned short	timer_tmr2;	/* timer 2 mode reg */
	volatile unsigned short	timer_tmr1;	/* timer 1 mode reg */
	volatile unsigned short	timer_trr2;	/* timer 2 referance reg */
	volatile unsigned short	timer_trr1;	/* timer 1 referance reg */
	volatile unsigned short	timer_tcr2;	/* timer 2 capture reg */
	volatile unsigned short	timer_tcr1;	/* timer 1 capture reg */
	volatile unsigned short	timer_tcn2;	/* timer 2 counter reg */
	volatile unsigned short	timer_tcn1;	/* timer 1 counter reg */
	volatile unsigned short	timer_tmr4;	/* timer 4 mode reg */
	volatile unsigned short	timer_tmr3;	/* timer 3 mode reg */
	volatile unsigned short	timer_trr4;	/* timer 4 referance reg */
	volatile unsigned short	timer_trr3;	/* timer 3 referance reg */
	volatile unsigned short	timer_tcr4;	/* timer 4 capture reg */
	volatile unsigned short	timer_tcr3;	/* timer 3 capture reg */
	volatile unsigned short	timer_tcn4;	/* timer 4 counter reg */
	volatile unsigned short	timer_tcn3;	/* timer 3 counter reg */
	volatile unsigned short	timer_ter2;	/* timer 2 event reg */
	volatile unsigned short	timer_ter1;	/* timer 1 event reg */
	volatile unsigned short	timer_ter4;	/* timer 4 event reg */
	volatile unsigned short	timer_ter3;	/* timer 3 event reg */
	volatile unsigned char	RESERVED23[0x8];	/* Reserved area */

/* CP */
	volatile unsigned char	RESERVED24[0x2];	/* Reserved area */
	volatile unsigned short	cp_cr;		/* command register */

	volatile unsigned char	cp_resv1;	/* Reserved reg */
	volatile unsigned char	RESERVED25;	/* Reserved area */
	volatile unsigned short	cp_rccr;	/* main configuration reg */

	volatile unsigned long	cp_resv2;	/* Reserved reg */

	volatile unsigned short	cp_rctr2;	/* ram break register 2 */
	volatile unsigned short	cp_rctr1;	/* ram break register 1 */

	volatile unsigned short	cp_rctr4;	/* ram break register 4 */
	volatile unsigned short	cp_rctr3;	/* ram break register 3 */

	volatile unsigned short	cp_rter;	/* RISC timers event reg */
	volatile unsigned char	RESERVED26[0x2];	/* Reserved area */

	volatile unsigned short	cp_rtmr;	/* RISC timers mask reg */
	volatile unsigned char	RESERVED27[0x2];	/* Reserved area */

	volatile unsigned char	RESERVED28[0x14];	/* Reserved area */

/* BRG */
	volatile unsigned long	brgc1;		/* BRG1 configuration reg */
	volatile unsigned long	brgc2;		/* BRG2 configuration reg */
	volatile unsigned long	brgc3;		/* BRG3 configuration reg */
	volatile unsigned long	brgc4;		/* BRG4 configuration reg */
/* SCC registers */
	struct scc_regs {
		volatile unsigned long	scc_gsmra; /* SCC general mode reg */
		volatile unsigned long	scc_gsmrb; /* SCC general mode reg */

		volatile unsigned char	RESERVED29[0x2]; /* Reserved area */
		volatile unsigned short	scc_psmr;  /* protocol specific mode register */
		volatile unsigned short	scc_dsr;   /* SCC data sync reg */
		volatile unsigned short	scc_todr;  /* SCC transmit on demand */

		volatile unsigned char	RESERVED30[0x2];/* Reserved area */
		volatile unsigned short	scc_scce;	/* SCC event reg */

		volatile unsigned char	scc_sccs;	/* SCC status reg */
		volatile unsigned char	RESERVED31[0x1];/* Reserved area */
		volatile unsigned short	scc_sccm;	/* SCC mask reg */

		volatile unsigned char	RESERVED32[0x8]; /* Reserved area */
	} scc_regs[2], scc_null[2];
/* SMC */
	struct smc_regs smc_regs[2];
/* SPI */
	volatile unsigned char	RESERVED38a[0x2]; /* Reserved area */
	volatile unsigned short	spi_spmode;	      /* SPI mode reg */

	volatile unsigned char	RESERVED39a[0x1]; /* Reserved area */
	volatile unsigned char	spi_spie;	      /* SPI event reg */
	volatile unsigned char	RESERVED38b[0x2]; /* Reserved area */

	volatile unsigned char	RESERVED40a[0x1];	/* Reserved area */
	volatile unsigned char	spi_spim;	/* SPI mask reg */
	volatile unsigned char	RESERVED39b[0x2];	/* Reserved area */

	volatile unsigned char	RESERVED41a[0x2];	/* Reserved area */
	volatile unsigned char	spi_spcom;	/* SPI command reg */
	volatile unsigned char	RESERVED40b[0x1];	/* Reserved area */

/* PIP */
	volatile unsigned short	pip_pipc;	/* pip configuration reg */
	volatile unsigned char	RESERVED41b[0x2];	/* Reserved area */

	volatile unsigned short	pip_ptpr;	/* pip timing parameters reg */
	volatile unsigned char	RESERVED42[0x2];	/* Reserved area */

	volatile unsigned long	pip_pbdir;	/* port b data direction reg */
	volatile unsigned long	pip_pbpar;	/* port b pin assignment reg */

	volatile unsigned char	RESERVED43[0x2];	/* Reserved area */
	volatile unsigned short	pip_pbodr;	/* port b open drain reg */

	volatile unsigned long	pip_pbdat;	/* port b data reg */

	volatile unsigned char	RESERVED44[0x18];	/* Reserved area */

/* Serial Interface */
	volatile unsigned long	si_simode;	/* SI mode register */

	volatile unsigned char	si_sicmr;	/* SI command register */
	volatile unsigned char	si_sistr;	/* SI status register */
	volatile unsigned char	RESERVED45; /* Reserved area */
	volatile unsigned char	si_sigmr;	/* SI global mode register */

	volatile unsigned char	RESERVED46[0x4]; /* Reserved area */

	volatile unsigned long	si_sicr;	/* SI clock routing */
	volatile unsigned long	si_sirp;	/* SI ram pointers */

	volatile unsigned char	RESERVED47[0x10c]; /* Reserved area */

	volatile unsigned short	si_siram[0x100]; /* SI routing ram */

	volatile unsigned short	lcda_lcolr[0x100];/* lcd color Ram for Rev A.X */

	volatile unsigned char	RESERVED48[0x1000]; /* Reserved area */

/* BASE + 0x2000: user data memory */
	volatile unsigned char	udata_bd_ucode[0x400];	/*user data bd's Ucode*/
	volatile unsigned char	udata_bd_ucode2[0x400];	/*user data bd's Ucode*/
	volatile unsigned char	udata_bd[0x600];	    /*user data Ucode*/
	volatile unsigned char	ucode_ext2[0x100];	/*Extension ram for ucode2 */
	volatile unsigned char	ucode_ext[0x100];	/*Extension ram for ucode  */
	volatile unsigned char	RESERVED49[0xC00];	/* Reserved area */

/* BASE + 0x3c00: PARAMETER RAM */
	union {
		struct scc_pram {
			union {
				struct hdlc_pram	h;
				struct uart_pram	u;
				struct bisync_pram	b;
				struct transparent_pram	t;
				struct async_hdlc_pram	a;
				unsigned char	RESERVED50[0x80];
			} pscc;		/* scc parameter area (protocol dependent) */
			union {
				struct {
					struct i2c_pram	i2c;
					unsigned char	RESERVED56[0x18];
					struct idma_pram	idma1;
				} i2c_idma;
				struct {
					struct spi_pram	spi;
					unsigned char	RESERVED57[0x8];
					struct timer_pram	timer;
					struct idma_pram	idma2;
				} spi_timer_idma;
				struct {
					union {
						smc_uart_pram u;
						smc_trnsp_pram t;
						centronics_pram c;
					} psmc;
					unsigned char	modem_param[0x40];
				} smc_modem;
				struct {
					unsigned char   RESERVED54[0x30]; 
					struct ucode_pram	ucode;
				} pucode;
			} pothers;
		} scc;
		struct ethernet_pram	enet_scc;
		unsigned char	pr[0x100];
	} pram[4];

} PDA;

#endif // ASM_ONLY

//
// Define MPC8xx Special Purpose Registers
//

#define PVR        287      // Processor Version Reg.
#define DEC         22      // Decrementer Reg.
#define SRR1        27      // Save/Restore Register 1
#define ICR        148      // Instruction Compare Reg.
#define DER        149      // Debug Enable Reg.
#define ICTRL      158      // Instruction Support Control Reg.
#define IC_CST     560      // I-Cache Control/Status Reg.
#define IC_ADR     561      // I-Cache Address Reg.
#define IC_DAT     562      // I-Cache Data Reg.
#define DC_CST     568      // D-Cache Control/Status Reg.
#define DC_ADR     569      // D-Cache Address Reg.
#define DC_DAT     570      // D-Cache Data Reg.
#define IMMR       638      // Internal Memory Map Reg.
#define EIE         80      // External Interrupt Enable Reg.
#define EID         81      // External Interrupt Disable Reg.


//
// Define internal register offsets from IMMR.
//

#define MEMC_BR1_OFFSET 0x108

#define MDR_OFFSET  0x17c
#define MCR_OFFSET  0x168

#define BR0_OFFSET  0x100
#define OR0_OFFSET  0x104
#define BR1_OFFSET  0x108
#define OR1_OFFSET  0x10c
#define BR2_OFFSET  0x110
#define OR2_OFFSET  0x114
#define BR3_OFFSET  0x118
#define OR3_OFFSET  0x11c
#define MAMR_OFFSET 0x170
#define SCCR_OFFSET   0x280
#define PLPRCR_OFFSET 0x284
#define SIUMCR_OFFSET 0
#define SYPCR_OFFSET 4
#define RTCSC_OFFSET 0x220

#define MPTPR_OFFSET 0x178
#define TBSCR_OFFSET 0x202
#define PISCR_OFFSET 0x242