reg4102.h

WINDOWS CE BSP用于SBC2440开发板

#define BattLockIntr    (1<<7)      // battery lock interrupt
#define CardLockIntr    (1<<6)      // card lock interrupt
#define TimeoutRstIntr  (1<<5)      // HAL timer reset interrupt
#define RTCRSTIntr      (1<<4)      // RTC reset interrupt
#define RSTSWIntr       (1<<3)      // reset switch interrupt
#define DMSRSTIntr      (1<<2)      // deadman's switch interrupt
#define BattIntr        (1<<1)      // battery alarm interrupt
#define PowerSWIntr     (1<<0)      // power switch interrupt

// RTCINTREG
#define RTCIntr3        (1<<3)      // TCLK timer interrupt
#define RTCIntr2        (1<<2)      // RTC long 2 interrupt
#define RTCIntr1        (1<<1)      // RTC long 1 interrupt
#define RTCIntr0        (1<<0)      // Elapsed timer interrupt

// GIU interrupts
#define DCDChgIntr      (1<<15)     // DCD signal change interrupt
#define BcklightIntr    (1<<8)      // Backlight switch interrupt
#define DebugIntr       (1<<7)      // Interrupt from debug board
#define PCMCIAIntr      (1<<6)      // PCMCIA interrupt
#define PanelIntr       (1<<3)      // Touch panel cover interrupt
#define NotifyIntr      (1<<2)      // Notification switch interrupt
#define BatLockIntr     (1<<0)      // Battery lock switch interrupt

// PIU interrupt
#define PadCmdIntr      (1<<6)      // PIU command scan interrupt
#define PadADPIntr      (1<<5)      // PIU AD port scan interrupt
#define PadPage1Intr    (1<<4)      // PIU data buffer page 1 interrupt
#define PadPage0Intr    (1<<3)      // PIU data buffer page 0 interrupt
#define PadDLostIntr    (1<<2)      // PIU data lost interrupt
#define PenChgIntr      (1<<0)      // PIU pen change interrupt

// AIU interrupt
#define SPEndIntr       (1<<3)      // Speaker DMA 2 page interrupt
#define SPIntr          (1<<2)      // Speaker DMA 1 page interrupt
#define SPIdleIntr      (1<<1)      // Speaker idle interrupt

// KIU interrupt
#define KDatLostIntr    (1<<2)      // KIU key data lost interrupt
#define KDatRdyIntr     (1<<1)      // KIU key data scan interrupt
#define KScanIntr       (1<<0)      // KIU key scan interrupt

// Interrupts groupe
#define INTRGRP_TOUCH   (PadADPIntr | PadPage1Intr | PadPage0Intr | PadDLostIntr)
#define INTRGRP_KEY     (KDatLostIntr | KDatRdyIntr)
#define INTRGRP_AUDIO   (SPEndIntr | SPIntr | SPIdleIntr)
#define INTRGRP_GPIO    (BcklightIntr | NotifyIntr | BatLockIntr)
#define INTRGRP_POW     (PowerIntr | BatIntr)

//
// PMU control bits
//
#define GPIO3MSK        (1<<15)
#define GPIO2MSK        (1<<14)
#define GPIO1MSK        (1<<13)
#define GPIO0MSK        (1<<12)
#define GPIO3TRG        (1<<11)
#define GPIO2TRG        (1<<10)
#define GPIO1TRG        (1<<9)
#define GPIO0TRG        (1<<8)
#define STANDBYMOD      (1<<7)
#define HALTIMERRST     (1<<2)

/* DSU registers */
// redef error
//#define DSU_BASE         0xab0000e0   // DSU register base address
#define DSUCNTREG        0x00       // DSU control register
#define DSUSETREG        0x02       // DSU read time set register
#define DSUCLRREG        0x04       // DSU clear register
#define DSUTIMREG        0x06       // DSU elapsed time register
#define DSULOADREG       0x08       // DSU count register


// GPIO ports
#define DCDChg          (1<<15)
#define RSPWR1          (1<<14)
#define IRPWR1          (1<<13)
#define AMPPWR1         (1<<12)
#define LCDDPWR1        (1<<11)
#define LCDPWR11        (1<<10)
#define Bcklight        (1<<8)

/* Serial I/O registers */
#define SIU_BASE         0xab000140    // SIU register base address
#define SIURXDATREG      0x00       // SIU Rx data register
#define SIUTXDATREG      0x02       // SIU Tx data register
#define SIUCNTREG        0x04       // SIU control register
#define SIUDLENGTHREG    0x06       // SIU RxTx data length register
#define SIUINTREG        0x08       // SIU interrupt register
#define SIURS232CREG     0x0a       // SIU RS232C control register
#define SIUBAUDSELREG    0x0c       // SIU baudrate select register



/* PCMCIA Controller registers */
#define PCMCIA_BASE4102  0xb40003e0      //  PCMCIA control register base address
#define INDEXREG         0x00           // PCMCIA index register
#define DATAREG          0x01           // DATA write register for PCMCIA



// SOFT interrupt
// #define SoftIntr         0x0001  /* INTB interrupt  :rename or not? */

// NMI
#define NMIorINT         0x0001     /* BatIntr is NMI or INTB */

//
// Interrupt Clear Register & Bit  (W1C)
//

/* LCD display register */
#define DISP_BASE4102       0xa0000000  // LCD memory base address
                                       // VRAM area = 0x0a000000 - 0x0a1fffff(h)

// PMUINTREG
#define BatIntr_clr          0x0002     // PMUINTREG writing
#define PowerIntr_clr        0x0001     // PMUINTREG writing

// RTC Unit
#define RtcLongIntr_clr      0x0001     // RTCINTREG writing
#define AlarmIntr_clr        0x0002     // RTCINTREG writing (ElapseTimeIntr)

//PCMCIA controller
#define IsaIntr_clr_index     0x83      // PCMCIA controler's index register writing
#define IsaIntr_clr           0x0       // PCMCIA controler's DATA register writing

// PIU Unit
#define PIUIntr_clr          0x001f     // PIUINTREG writing

// ADU Unit
#define ADUIntr_clr          0x000f     // ADUINTRREG writing

// KIU Unit
#define KIUIntr_clr          0x001f     // KIUINTREG writing

// GIU Unit
#define GIsmUIntr_clr          0x1fff     // GIUINTSTREG writing

// SIU Unit
#define SIUIntr_clr          0x07ff    // SIUINTREG writing

// BCU Unit
#define BERRST              (1<<0)      // bus error reset

// Software interrupt
#define SoftIntr_clr         0x0000    // SOFTINTREG(0xab00009a) writing

// args for InitGA()
#define COLDBOOT    0
#define WARMBOOT    1

#define SAVE_ICU_REGS

// CPU registers
#define REGCPU_AT       0x00
#define REGCPU_V0       0x04
#define REGCPU_V1       0x08
#define REGCPU_A0       0x0C
#define REGCPU_A1       0x10
#define REGCPU_A2       0x14
#define REGCPU_A3       0x18
#define REGCPU_T0       0x1C
#define REGCPU_T1       0x20
#define REGCPU_T2       0x24
#define REGCPU_T3       0x28
#define REGCPU_T4       0x2C
#define REGCPU_T5       0x30
#define REGCPU_T6       0x34
#define REGCPU_T7       0x38
#define REGCPU_S0       0x3C
#define REGCPU_S1       0x40
#define REGCPU_S2       0x44
#define REGCPU_S3       0x48
#define REGCPU_S4       0x4C
#define REGCPU_S5       0x50
#define REGCPU_S6       0x54
#define REGCPU_S7       0x58
#define REGCPU_T8       0x5C
#define REGCPU_T9       0x60
#define REGCPU_K0       0x64
#define REGCPU_K1       0x68
#define REGCPU_GP       0x6C
#define REGCPU_SP       0x70
#define REGCPU_S8       0x74
#define REGCPU_RA       0x78

// CP0 registers
#define REGCP0_INDEX        0x80
#define REGCP0_RANDOM       0x84
#define REGCP0_ENTRYLO0     0x88
#define REGCP0_ENTRYLO1     0x8C
#define REGCP0_CONTEXT      0x90
#define REGCP0_PAGEMASK     0x94
#define REGCP0_WIRED        0x98
#define REGCP0_COUNT        0x9C
#define REGCP0_ENTRYHI      0xA0
#define REGCP0_COMPARE      0xA4
#define REGCP0_PSR      0xA8
#define REGCP0_CAUSE        0xAC
#define REGCP0_EPC      0xB0
#define REGCP0_CONFIG       0xB4
#define REGCP0_LLADDR       0xB8
#define REGCP0_WATCHLO      0xBC
#define REGCP0_XCONTEXT     0xC0
#define REGCP0_PERR     0xC4
#define REGCP0_TAGLO        0xC8
#define REGCP0_TAGHI        0xCC
#define REGCP0_ERROREPC     0xD0

#ifdef SAVE_ICU_REGS
#define REGGA_MSYSINTREG    0x100
#define REGGA_MPIUINTREG    0x102
#define REGGA_MAIUINTREG    0x104
#define REGGA_MKIUINTREG    0x106
#define REGGA_MGIUINTREG    0x108
#define REGGA_MDSIUINTREG   0x10A
#define REGGA_MSYSINTREG2   0x10C
#define REGGA_MGIUINTHREG   0x10E
#define REGGA_MFIRINTHREG   0x110
#endif