📄 reg4102.h
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// Copyright (c) 1999-2000 Microsoft Corporation. All rights reserved.
/* Defines for Reference Platform control registers ( Read-only ) */
//
// Definition of ASIC register base address
//
#define REGISTERBASE 0xab000000 // ASIC I/O register base address
#define BCU_BASE (REGISTERBASE + 0x0000) // BCU register base address
#define DMAAU_BASE (REGISTERBASE + 0x0020) // DMAAU register base address
#define DCU_BASE (REGISTERBASE + 0x0040) // DCU register base address
#define CMU_BASE (REGISTERBASE + 0x0060) // CMU register base address
#define ICU_BASE (REGISTERBASE + 0x0080) // ICU register base address
#define PMU_BASE (REGISTERBASE + 0x00a0) // PMU register base address
#define RTC_BASE (REGISTERBASE + 0x00c0) // RTC register base address
#define DSU_BASE (REGISTERBASE + 0x00e0) // DSU register base address
#define GIU_BASE (REGISTERBASE + 0x0100) // GIU register base address
#define PIU_BASE (REGISTERBASE + 0x0120) // PIU register base address
#define AIU_BASE (REGISTERBASE + 0x0160) // AIU register base address
#define KIU_BASE (REGISTERBASE + 0x0180) // KIU register base address
#define RTC_BASE2 (REGISTERBASE + 0x01c0) // RTC2 register base address
#define ICU_BASE2 (REGISTERBASE + 0x0200) // ICU2 register base address
#define LED_BASE (REGISTERBASE + 0x0240) // LED register base address
#define PIU_BASE2 (REGISTERBASE + 0x02a0) // PIU2 register base address
// BCU registers
#define BCUCNTREG 0x00 // BCU control register 1
#define BCUCNTREG2 0x02 // BCU control register 2
#define BCUSPEEDREG 0x0a // BCU access cycle change register
#define BCUERRSTREG 0x0c // BCU BUS error status register
#define BCURFCNTREG 0x0e // BCU refresh control register
#define REVIDREG 0x10 // revision ID register
#define BCURFCOUNTREG 0x12 // BCU refresh count register
#define CLKSPEEDREG 0x14 // clock speed register
// DMAAU registers
#define AIUIBALREG 0x00 // AIU IN DMA base address register low
#define AIUIBAHREG 0x02 // AIU IN DMA base address register high
#define AIUIALREG 0x04 // AIU IN DMA address register low
#define AIUIAHREG 0x06 // AIU IN DMA address register high
#define AIUOBALREG 0x08 // AIU OUT DMA base address register low
#define AIUOBAHREG 0x0a // AIU OUT DMA base address register high
#define AIUOALREG 0x0c // AIU OUT DMA address register low
#define AIUOAHREG 0x0e // AIU OUT DMA address register high
#define FIRBALREG 0x10 // FIR DMA base address register low
#define FIRBAHREG 0x12 // FIR DMA base address register high
#define FIRALREG 0x14 // FIR DMA address register low
#define FIRAHREG 0x16 // FIR DMA address register high
// DCU registers
#define DMARSTREG 0x00 // DMA reset register
#define DMAIDLERG 0x02 // DMA idle register
#define DMASENREG 0x04 // DMA sequencer enable register
#define DMAMSKREG 0x06 // DMA mask register
#define DMAREQREG 0x08 // DMA request register
#define DMATDREG 0x0a // DMA transfer direction register
// CMU registers
#define CMUCLKMSK 0x00 // CMU clock mask register
// ICU registers
#define ICU_SYSINTREG 0x00 // system interrupt register
#define ICU_PIUINTREG 0x02 // PIU interrupt register
#define ICU_AIUINTREG 0x04 // AIU interrupt register
#define ICU_KIUINTREG 0x06 // KIU interrupt register
#define ICU_GIUINTREG 0x08 // GIU interrupt register
#define ICU_DSIUINTREG 0x0a // DSIU interrupt register
#define ICU_MSYSINTREG 0x0c // system interrupt mask register
#define ICU_MPIUINTREG 0x0e // PIU interrupt mask register
#define ICU_MAIUINTREG 0x10 // AIU interrupt mask register
#define ICU_MKIUINTREG 0x12 // KIU interrupt mask register
#define ICU_MGIUINTREG 0x14 // GPIO[15:0] interrupt mask register
#define ICU_MDSIUINTREG 0x16 // DSIU interrupt mask register
#define ICU_NMIREG 0x18 // NMI register
#define ICU_SOFTINTREG 0x1a // software interrupt register
// ICU2 register
#define ICU_SYSINT2REG 0x00 // system interrupt 2 register
#define ICU_GIUINTHREG 0x02 // GPIO[31:16] interrupt register
#define ICU_FIRINTHREG 0x04 // FIR interrupt register
#define ICU_MSYSINT2REG 0x06 // system interrupt mask 2 register
#define ICU_MGIUINTHREG 0x08 // GPIO [31:16] interrupt mask register
#define ICU_MFIRINTHREG 0x0a // FIR interrupt mask register
// PMU registers
#define PMUINTREG 0x00 // PMU interrupt/status register
#define PMUCNTREG 0x02 // PMU control register
// RTC registers
#define ETIMELREG 0x00 // Elapsed time [15:0] register
#define ETIMEMREG 0x02 // Elapsed time [31:16] register
#define ETIMEHREG 0x04 // Elapsed time [47:32] register
#define ECMPLREG 0x08 // Elapsed compare [15:0] register
#define ECMPMREG 0x0a // Elapsed compare [31:16] register
#define ECMPHREG 0x0c // Elapsed compare [47:32] register
#define RTCLLREG 0x10 // RTC long 1 [15:0] register
#define RTCLHREG 0x12 // RTC long 1 [23:16] register
#define RTCLCNTLREG 0x14 // RTC long 1 count [15:0] register
#define RTCLCNTHREG 0x16 // RTC ling 1 count [23:16] register
#define RTCL2LREG 0x18 // RTC long 2 [15:0] register
#define RTCL2HREG 0x1a // RTC long 2 [23:16] register
#define RTCL2CNTLREG 0x1c // RTC long 2 count [15:0] register
#define RTCL2CNTHREG 0x1e // RTC ling 2 count [23:16] register
#define TCLKLREG 0x00 // TCLK [15:0] register
#define TCLKHREG 0x02 // TCLK [24:16] register
#define TCLKCNTLREG 0x04 // TCLK count [15:0] register
#define TCLKCNTHREG 0x06 // TCLK count [24:16] register
#define RTCINTREG 0x1e // RTC interrupt register
// GIU registers
#define GIUIOSELL 0x00 // GPIO[15:0] input/output select register
#define GIUIOSELH 0x02 // GPIO[31:16] input/output select register
#define GIUPIODL 0x04 // GPIO[15:0] input/output data register
#define GIUPIODH 0x06 // GPIO[31:16] input/output data register
#define GIUINTSTATL 0x08 // GPIO[15:0] interrupt status register
#define GIUINTSTATH 0x0a // GPIO[31:16] interrupt status register
#define GIUINTENL 0x0c // GPIO[15:0] interrupt enable register
#define GIUINTENH 0x0e // GPIO[31:16] interrupt enable register
#define GIUINTTYPL 0x10 // GPIO[15:0] interrupt type select register
#define GIUINTTYPH 0x12 // GPIO[31:16] interrupt type select register
#define GIUINTALSELL 0x14 // GPIO[15:0] interrupt active level select register
#define GIUINTALSELH 0x16 // GPIO[31:16] interrupt active level select register
#define GIUINTHTSELL 0x18 // GPIO[15:0] interrupt hold/through select register
#define GIUINTHTSELH 0x1a // GPIO[31:16] interrupt hold/through select register
#define GIUPODATL 0x1c // GPIO[32:47] output data register
#define GIUPODATH 0x1e // GPIO[49:48] output data register
// PIU registers
#define PIUCNTREG 0x02 // PIU control register
#define PIUINTREG 0x04 // PIU interrupt cause register
#define PIUSIVLREG 0x06 // PIU data sampling interval register
#define PIUSTBLREG 0x08 // PIU AD converter start delay register
#define PIUCMDREG 0x0a // PIU AD command register
#define PIUASCNREG 0x10 // PIU AD port scan register
#define PIUAMSKREG 0x12 // PIU AD scan mask register
#define PIUCIVLREG 0x1e // PIU check interval register
#define PIUPB00REG 0x00 // PIU page buffer 00 register
#define PIUPB01REG 0x02 // PIU page buffer 01 register
#define PIUPB02REG 0x04 // PIU page buffer 02 register
#define PIUPB03REG 0x06 // PIU page buffer 03 register
#define PIUPB10REG 0x08 // PIU page buffer 10 register
#define PIUPB11REG 0x0a // PIU page buffer 11 register
#define PIUPB12REG 0x0c // PIU page buffer 12 register
#define PIUPB13REG 0x0e // PIU page buffer 13 register
#define PIUAB0REG 0x10 // PIU AD scan buffer 0 rgister
#define PIUAB1REG 0x12 // PIU AD scan buffer 1 rgister
#define PIUAB2REG 0x14 // PIU AD scan buffer 2 rgister
#define PIUAB3REG 0x16 // PIU AD scan buffer 3 rgister
#define PIUPB04REG 0x1c // PIU page buffer 04 register
#define PIUPB14REG 0x1e // PIU page buffer 14 register
// AIU registers
#define SDMADATREG 0x00 // speaker DMA data register
#define MDMADATREG 0x02 // mike DMA data register
#define SODATREG 0x06 // speaker output data register
#define SCNTREG 0x08 // speaker output control register
#define SCNVRREG 0x0a // speaker conversion rate register
#define SCNVCUNTREG 0x0c // speaker conversion count register
#define MIDATREG 0x10 // mike input data register
#define MCNTREG 0x12 // mike input control register
#define MCNVRREG 0x14 // mike conversion rate register
#define MCNVCUNTREG 0x16 // mike conversion count register
#define DVALIDREG 0x18 // data valid register
#define SEQREG 0x1a // sequential register
#define INTREG 0x1c // interrupt register
// KIU registers
#define KIUDAT0 0x00 // KIU data0 register
#define KIUDAT1 0x02 // KIU data1 register
#define KIUDAT2 0x04 // KIU data2 register
#define KIUDAT3 0x06 // KIU data3 register
#define KIUDAT4 0x08 // KIU data4 register
#define KIUDAT5 0x0a // KIU data5 register
#define KIUSCANREP 0x10 // KIU scan/repeat register
#define KIUSCANS 0x12 // KIU scan status register
#define KIUWKS 0x14 // KIU wait keyscan stable register
#define KIUWKI 0x16 // KIU wait keyscan interval register
#define KIUINT 0x18 // KIU interrupt register
#define KIURST 0x1a // KIU reset register
#define KIUGPEN 0x1c // KIU general purpose output enable register
#define SCANLINE 0x1e // KIU scan line register
// LED registers
#define LEDHTSREG 0x00 // LED H time set register
#define LEDLTSREG 0x02 // LED L time set register
#define LEDHLTCLREG 0x04 // LED hi time count L register
#define LEDHLTCHREG 0x06 // LED hi time count H register
#define LEDCNTREG 0x08 // LED control register
#define LEDASTCREG 0x0a // LED auto stop time count register
#define LEDINTREG 0x0c // LED interrupt register
// SYSINTREG
#define DozePIUIntr (1<<13) // Doze PIU interrupt
#define SoftIntr (1<<11) // Software interrupt
#define WrberrIntr (1<<10) // write back bus error interrupt
#define SIUIntr (1<<9) // SIU interrupt
#define GIUIntr (1<<8) // GIU interrupt
#define KIUIntr (1<<7) // KIU interrupt
#define AIUIntr (1<<6) // AIU interrupt
#define PIUIntr (1<<5) // PIU interrupt
#define EtimerIntr (1<<3) // elapsed timer interrupt
#define RtcLongIntr (1<<2) // RTC Long 1 interrupt
#define PowerIntr (1<<1) // power switch interrupt
#define BatIntr (1<<0) // battery alarm interrupt
// SYSINT2REG
#define DSIUIntr (1<<5) // DSIU interrupt
#define FIRIntr (1<<4) // FIR interrupt
#define TCLKIntr (1<<3) // TCLK interrupt
#define HSPIntr (1<<2) // HSP interrupt
#define LEDIntr (1<<1) // LED interrupt
#define RTCL2Intr (1<<0) // RTC long 2 interrupt
// PMUINTREG
#define GPIOIntr3 (1<<15) // GPIO[3] interrupt
#define GPIOIntr2 (1<<14) // GPIO[2] interrupt
#define GPIOIntr1 (1<<13) // GPIO[1] interrupt
#define GPIOIntr0 (1<<12) // GPIO[0] interrupt
#define DCDSTIntr (1<<10) // DCD signal interrupt
#define RTCIntr (1<<9) // elapsed timer interrupt
#define BATTINHIntr (1<<8) // BATTINH interrupt
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