r3912.h

WINDOWS CE BSP用于SBC2440开发板

/*++

Copyright (c) 1996-2000 Microsoft Corporation.  All rights reserved.

Module Name:

    r3912.h

Abstract:
    I/O definition for R3912 processor internal registers.

Environment:

    Kernel mode (unmapped) only

History:

Note:
   SHx base, MIPS R4100 base not supported.

 --*/

#ifndef _R3912_H_
#define _R3912_H_

/* Defines for Reference Platform control registers */

#define R3912_SYSTEM_ASIC_REGS_BASE	0xb0c00000	// for kseg1
#define R3912_PHYSICAL_ADDR_OFFSET 	0x10c00000
#define R3912_REGS_SIZE                 0x200
/*
   BIU Register
*/

#define OFF_BIU_MEM_CONFIG0		0x000
#define BIU_ENDCLKOUTTRI		(1 << 30)
#define BIU_DISDQMINIT			(1 << 29)
#define BIU_ENSDRAMPD			(1 << 28)
#define BIU_SHOWDINO			(1 << 27)
#define BIU_ENRMAP2			(1 << 26)
#define BIU_ENRMAP1			(1 << 25)
#define BIU_ENWRINPAGE			(1 << 24)
#define BIU_ENCS3USER			(1 << 23)
#define BIU_ENCS2USER			(1 << 22)
#define BIU_ENCS1USER			(1 << 21)
#define BIU_ENCS1DRAM			(1 << 20)
#define BIU_BANK1CONFMASK		(3 << 18)
#define BIU_BANK1CONF_16SDRAM		(3 << 18)	/* Bank 1 as 16 bit SDRAM */
#define BIU_BANK1CONF_8SDRAM		(2 << 18)	/* Bank 1 as 8 bit SDRAM */
#define BIU_BANK1CONF_32DRAM		(1 << 18)	/* Bank 1 as 32 bit DRAM/HDRAM */
#define BIU_BANK1CONF_16DRAM		(0 << 18)	/* Bank 1 as 16 bit DRAM/HDRAM */
#define BIU_BANK0CONFMASK		(3 << 16)
#define BIU_BANK0CONF_16SDRAM		(3 << 16)	/* Bank 1 as 16 bit SDRAM */
#define BIU_BANK0CONF_8SDRAM		(2 << 16)	/* Bank 1 as 8 bit SDRAM */
#define BIU_BANK0CONF_32DRAM		(1 << 16)	/* Bank 1 as 32 bit DRAM/HDRAM */
#define BIU_BANK0CONF_16DRAM		(0 << 16)	/* Bank 1 as 16 bit DRAM/HDRAM */
#define BIU_ROWSEL1MASK			(3 << 14)
#define BIU_ROWSEL1_TYPE1		(0 << 14)	/* Row Address 18, 17:9 */
#define BIU_ROWSEL1_TYPE2		(1 << 14)	/* Row Address 22,18,20,19,17:9 */
#define BIU_ROWSEL1_TYPE3		(2 << 14)	/* Row Address 22,21,19,17:9 */
#define BIU_ROWSEL1_TYPE4		(3 << 14)	/* Row Address 23,21,19,17:9 */
#define BIU_ROWSEL0MASK			(3 << 12)
#define BIU_ROWSEL0_TYPE1		(0 << 12)	/* Row Address 18, 17:9 */
#define BIU_ROWSEL0_TYPE2		(1 << 12)	/* Row Address 22,18,20,19,17:9 */
#define BIU_ROWSEL0_TYPE3		(2 << 12)	/* Row Address 22,21,19,17:9 */
#define BIU_ROWSEL0_TYPE4		(3 << 12)	/* Row Address 23,21,19,17:9 */
#define BIU_COLSEL1MASK			(0xf << 8)
#define BIU_COLSEL1_TYPE1		(0 << 8)	/* Column Address 22,20,18,8:1 */
#define BIU_COLSEL1_TYPE2		(1 << 8)	/* Column Address 19,18,8:2 */
#define BIU_COLSEL1_TYPE3		(2 << 8)	/* Column Address 21,20,8:2 */
#define BIU_COLSEL1_TYPE4		(3 << 8)	/* Column Address 23,22,20,18,8:2 */
#define BIU_COLSEL1_TYPE5		(4 << 8)	/* Column Address 24,22,20,18,8:2 */
#define BIU_COLSEL1_TYPE6		(5 << 8)	/* Column Address 18,p,X,8:0 */
#define BIU_COLSEL1_TYPE7		(6 << 8)	/* Column Address 22,p,X,21,8:1 */
#define BIU_COLSEL1_TYPE8		(7 << 8)	/* Column Address 18,p,X,21,8:1 */
#define BIU_COLSEL1_TYPE9		(8 << 8)	/* Column Address 22,p,X,23,21,8:2 */
#define BUI_COLSEL1_TYPE10		(9 << 8)	/* Column Address 21,8:2 */

#define BIU_COLSEL0MASK			(0xf << 4)
#define BIU_COLSEL0_TYPE1		(0 << 4)	/* Column Address 22,20,18,8:1 */
#define BIU_COLSEL0_TYPE2		(1 << 4)	/* Column Address 19,18,8:2 */
#define BIU_COLSEL0_TYPE3		(2 << 4)	/* Column Address 21,20,8:2 */
#define BIU_COLSEL0_TYPE4		(3 << 4)	/* Column Address 23,22,20,18,8:2 */
#define BIU_COLSEL0_TYPE5		(4 << 4)	/* Column Address 24,22,20,18,8:2 */
#define BIU_COLSEL0_TYPE6		(5 << 4)	/* Column Address 18,p,X,8:0 */
#define BIU_COLSEL0_TYPE7		(6 << 4)	/* Column Address 22,p,X,21,8:1 */
#define BIU_COLSEL0_TYPE8		(7 << 4)	/* Column Address 18,p,X,21,8:1 */
#define BIU_COLSEL0_TYPE9		(8 << 4)	/* Column Address 22,p,X,23,21,8:2 */
#define BIU_COLSEL0_TYPE10		(9 << 4)	/* Column Address 21,8:2 */

#define BIU_CS3SIZE			(1 << 3)
#define BIU_CS2SIZE			(1 << 2)
#define BIU_CS1SIZE			(1 << 1)
#define BIU_CS0SIZE			1

#define OFF_BIU_MEM_CONFIG1		0x0004
#define BIU_MCS3ACCVAL1MASK		(0xf << 28)
#define BIU_MCS3ACCVAL1(a)		(((a) << 28) & BIU_MCS3ACCVAL1MASK)
#define BIU_MCS3ACCVAL2MASK		(0xf << 24)
#define BIU_MCS3ACCVAL2(a)		(((a) << 24) & BIU_MCS3ACCVAL2MASK)
#define BIU_MCS2ACCVAL1MASK		(0xf << 20)
#define BIU_MCS2ACCVAL1(a)		(((a) << 20) & BIU_MCS3ACCVAL1MASK)
#define BIU_MCS2ACCVAL2MASK		(0xf << 16)
#define BIU_MCS2ACCVAL2(a)		(((a) << 16) & BIU_MCS2ACCVAL2MASK)
#define BIU_MCS1ACCVAL1MASK		(0xf << 12)
#define BIU_MCS1ACCVAL1(a)		(((a) << 12) & BIU_MCS1ACCVAL1MASK)
#define BIU_MCS1ACCVAL2MASK		(0xf << 8)
#define BIU_MCS1ACCVAL2(a)		(((a) << 8) & BIU_MCS1ACCVAL2MASK)
#define BIU_MCS0ACCVAL1MASK		(0xf << 4)
#define BIU_MCS0ACCVAL1(a)		(((a) << 4) & BIU_MCS0ACCVAL1MASK)
#define BIU_MCS0ACCVAL2MASK		0xf
#define BIU_MCS0ACCVAL2(a)		((a) & BIU_MCS0ACCVAL2MASK)

#define OFF_BIU_MEM_CONFIG2		0x0008
#define BIU_CS3ACCVAL1MASK		(0xf << 28)
#define BIU_CS3ACCVAL1(a)		(((a) << 28) & BIU_CS3ACCVAL1MASK)
#define BIU_CS3ACCVAL2MASK		(0xf << 24)
#define BIU_CS3ACCVAL2(a)		(((a) << 24) & BIU_CS3ACCVAL2MASK)
#define BIU_CS2ACCVAL1MASK		(0xf << 20)
#define BIU_CS2ACCVAL1(a)		(((a) << 20) & BIU_CS3ACCVAL1MASK)
#define BIU_CS2ACCVAL2MASK		(0xf << 16)
#define BIU_CS2ACCVAL2(a)		(((a) << 16) & BIU_CS2ACCVAL2MASK)
#define BIU_CS1ACCVAL1MASK		(0xf << 12)
#define BIU_CS1ACCVAL1(a)		(((a) << 12) & BIU_CS1ACCVAL1MASK)
#define BIU_CS1ACCVAL2MASK		(0xf << 8)
#define BIU_CS1ACCVAL2(a)		(((a) << 8) & BIU_CS1ACCVAL2MASK)
#define BIU_CS0ACCVAL1MASK		(0xf << 4)
#define BIU_CS0ACCVAL1(a)		(((a) << 4) & BIU_CS0ACCVAL1MASK)
#define BIU_CS0ACCVAL2MASK		0xf
#define BIU_CS0ACCVAL2(a)		((a) & BIU_CS0ACCVAL2MASK)

#define OFF_BIU_MEM_CONFIG3		0x00c
#define BIU_CARD2ACCVALMASK		(0xf << 28)
#define BIU_CARD2ACCVAL(a)		(((a) << 28) & BIU_CARD2ACCVALMASK)
#define BIU_CARD1ACCVALMASK		(0xf << 24)
#define BIU_CARD1ACCVAL(a)		(((a) << 24) & BIU_CARD1ACCVALMASK)
#define BIU_CARD2IOACCVALMASK		(0xf << 20)
#define BIU_CARD2IOACCVAL(a)		(((a) << 20) & BIU_CARD2IOACCVALMASK)
#define BIU_CARD1IOACCVALMASK		(0xf << 16)
#define BIU_CARD1IOACCVAL(a)		(((a) << 16) & BIU_CARD1IOACCVALMASK)
#define BIU_ENMCS3PAGE			(1 << 15)
#define BIU_ENMCS2PAGE			(1 << 14)
#define BIU_ENMCS1PAGE			(1 << 13)
#define BIU_ENMCS0PAGE			(1 << 12)
#define BIU_ENCS3PAGE			(1 << 11)
#define BIU_ENCS2PAGE			(1 << 10)
#define BIU_ENCS1PAGE			(1 << 9)
#define BIU_ENCS0PAGE			(1 << 8)
#define BIU_CARD2WAITEN			(1 << 7)
#define BIU_CARD1WAITEN			(1 << 6)
#define BIU_CARD2IOEN			(1 << 5)
#define BIU_CARD1IOEN			(1 << 4)
#define BIU_PORT8SEL			(1 << 3)

#define OFF_BIU_MEM_CONFIG4		0x010
#define BIU_ENBANK1HDRAM		(1 << 31)
#define BIU_ENBANK0HDRAM		(1 << 30)
#define BIU_ENARB			(1 << 29)
#define BIU_DISSNOP			(1 << 28)
#define BIU_CLRWRBUSERRINT		(1 << 27)
#define BIU_ENBANK1OPT			(1 << 26)
#define BIU_ENBANK0OPT			(1 << 25)
#define BIU_ENWATCH			(1 << 24)
#define BIU_WATCHTIMEVALMASK		(0xf << 20)
#define BIU_WATCHTIMEVAL(a)		(((a) << 20) & BIU_WATCHTIMEVALMASK)
#define BIU_MEMPOWERDOWN		(1 << 16)
#define	BIU_ENRFSH1			(1 << 15)
#define	BIU_ENRFSH0			(1 << 14)
#define BIU_RFSHVAL1MASK		(0x1f << 8)
#define BIU_RFSHVAL1(a)			(((a) << 8) & BIU_RFSHVAL1MASK)
#define BIU_RFSHVAL2MASK		0x1f
#define BIU_RFSHVAL2(a)			((a) & BIU_RFSHVAL2MASK)

#define OFF_BIU_MEM_CONFIG5		0x014
#define BIU_STARTVAL2MASK		0xfffffe00
#define BIU_MASK2			0x0000000f

#define OFF_BIU_MEM_CONFIG6		0x018
#define BIU_STARTVAL1MASK		0xfffffe00
#define BIU_MASK1			0x0000000f

#define OFF_BIU_MEM_CONFIG7		0x01c
#define BIU_RMAPADD2MASK		0xfffffe00

#define OFF_BIU_MEM_CONFIG8		0x020
#define BIU_RMAPADD1MASK		0xfffffe00

/*
   SIU Module
*/
#ifdef INTERNAL_TEST
#define OFF_SIU_TEST			0x1c8
#define SIU_ENDMATEST			(1 << 7)
#define SIU_ENNOTIMETEST		(1 << 6)
#define SIU_DMATESTWRMASK		(0x3f)
#endif /* INTERNAL_TEST */

/*
  R3912 Clock Module 
*/

#define OFF_CLOCK_CTL			0x1c0
#define CLOCK_CHICLKDIVMASK		0xff000000
#define CLOCK_CHICLKDIV(a)		((a) << 24)
#define CLOCK_ENCLKTEST			(1 << 23)
#define CLOCK_TESTSELSIB		(1 << 22)
#define CLOCK_CHIMCLKSEL		(1 << 21)
#define CLOCK_CHICLKDIR			(1 << 20)
#define CLOCK_ENCHIMCLK			(1 << 19)
#define CLOCK_ENVIDCLK			(1 << 18)
#define CLOCK_ENMSUBCLK			(1 << 17)
#define CLOCK_ENSPICLK			(1 << 16)
#define CLOCK_ENTIMERCLK		(1 << 15)
#ifdef INTERNAL_TEST
#define CLOCK_FASTTIMERCLK		(1 << 14)
#endif /* INTERNAL_TEST */
#define CLOCK_SIBMCLKDIR		(1 << 13)
#define CLOCK_ENSIBMCLK			(1 << 11)
#define CLOCK_SIBMCLKDIVMASK		0x00000700
#define CLOCK_SIBMCLKDIV(a)		(((a) << 8) & CLOCK_SIBMCLKDIVMASK)
#define CLOCK_ENCSERSEL			(1 << 7)
#define CLOCK_CSERDIVMASK		0x00000070
#define CLOCK_CSERDIV(a)		(((a) << 4) & CLOCK_CSERDIVMASK)
#define CLOCK_ENCSERCLK			(1 << 3)
#define CLOCK_ENIRCLK			(1 << 2)
#define CLOCK_ENUARTACLK		(1 << 1)
#define CLOCK_ENUARTBCLK		1

/*
   CHI Module
*/
#define OFF_CHI_CTL			0x1d8
#define CHI_CHILOOP			(1 << 29)
#ifdef INTERNAL_TEST
#define CHI_CHIENTEST			(1 << 28)
#endif /* INTERNAL_TEST */
#define CHI_CHIFSDIR			(1 << 27)
#define CHI_CHIFSWIDEMASK		(3 << 25)
#define CHI_CHIFSWIDE_1BIT		0
#define CHI_CHIFSWIDE_2BIT		(1 << 25)
#define CHI_CHIFSWIDE_1BYTE		(2 << 25)
#define CHI_CHIFSWIDE_NCHAN		(3 << 25)
#define CHI_CHINCHANMASK		(0x1f << 20)
#define CHI_CHINCHAN(a)			(((a) << 20) & CHI_CHINCHANMASK)
#define CHI_CHITXBOFFMASK		(0xf << 16)
#define CHI_CHITXBOFF(a)		(((a) << 16) & CHI_CHITXBOFFMASK)
#define CHI_CHIRXBOFFMASK		(0xf << 12)
#define CHI_CHIRXBOFF(a)		(((a) << 12) & CHI_CHIRXBOFFMASK)
#define CHI_TXMSBFIRST			(1 << 11)
#define CHI_RXMSBFIRST			(1 << 10)
#define CHI_CHIRXFSPOL			(1 << 9)
#define CHI_CHITXFSPOL			(1 << 8)
#define CHI_CHIRXEDGE			(1 << 7)
#define CHI_CHITXEDGE			(1 << 6)
#define CHI_CHIFSEDGE			(1 << 5)
#define CHI_CHITXFSEDGE			(1 << 4)
#define CHI_CHICLK2XMODE		(1 << 3)
#define CHI_CHIRXEN			(1 << 2)
#define CHI_CHITXEN			(1 << 1)
#define CHI_ENCHI			1

#define OFF_CHI_PTREN			0x1dc
#define	CHI_CHITXPTRB3EN		(1 << 31)
#define	CHI_CHITXPTRB2EN		(1 << 30)
#define	CHI_CHITXPTRB1EN		(1 << 29)
#define	CHI_CHITXPTRB0EN		(1 << 28)
#define	CHI_CHITXPTRA3EN		(1 << 27)
#define	CHI_CHITXPTRA2EN		(1 << 26)
#define	CHI_CHITXPTRA1EN		(1 << 25)
#define	CHI_CHITXPTRA0EN		(1 << 24)
#define	CHI_CHIRXPTRB3EN		(1 << 23)
#define	CHI_CHIRXPTRB2EN		(1 << 22)
#define	CHI_CHIRXPTRB1EN		(1 << 21)
#define	CHI_CHIRXPTRB0EN		(1 << 20)
#define	CHI_CHIRXPTRA3EN		(1 << 19)
#define	CHI_CHIRXPTRA2EN		(1 << 18)
#define	CHI_CHIRXPTRA1EN		(1 << 17)
#define	CHI_CHIRXPTRA0EN		(1 << 16)

#define OFF_CHI_RCVPTRA			0x1e0
#define	CHI_CHIRXPTRA3MASK		(0xf << 24)
#define CHI_CHIRXPTRA3(a)		(((a) << 24) & CHI_CHIRXPTRA3MASK)
#define	CHI_CHIRXPTRA2MASK		(0xf << 16)
#define CHI_CHIRXPTRA2(a)		(((a) << 16) & CHI_CHIRXPTRA2MASK)
#define	CHI_CHIRXPTRA1MASK		(0xf << 8)
#define CHI_CHIRXPTRA1(a)		(((a) << 8) & CHI_CHIRXPTRA1MASK)
#define	CHI_CHIRXPTRA0MASK		0xf
#define CHI_CHIRXPTRA0(a)		((a) & CHI_CHIRXPTRA0MASK)

#define OFF_CHI_RCVPTRB			0x1e4
#define	CHI_CHIRXPTRB3MASK		(0xf << 24)
#define CHI_CHIRXPTRB3(a)		(((a) << 24) & CHI_CHIRXPTRB3MASK)
#define	CHI_CHIRXPTRB2MASK		(0xf << 16)
#define CHI_CHIRXPTRB2(a)		(((a) << 16) & CHI_CHIRXPTRB2MASK)
#define	CHI_CHIRXPTRB1MASK		(0xf << 8)
#define CHI_CHIRXPTRB1(a)		(((a) << 8) & CHI_CHIRXPTRB1MASK)
#define	CHI_CHIRXPTRB0MASK		0xf
#define CHI_CHIRXPTRB0(a)		((a) & CHI_CHIRXPTRB0MASK)

#define OFF_CHI_TXPTRA			0x1e8
#define	CHI_CHITXPTRA3MASK		(0xf << 24)
#define CHI_CHITXPTRA3(a)		(((a) << 24) & CHI_CHITXPTRA3MASK)
#define	CHI_CHITXPTRA2MASK		(0xf << 16)
#define CHI_CHITXPTRA2(a)		(((a) << 16) & CHI_CHITXPTRA2MASK)
#define	CHI_CHITXPTRA1MASK		(0xf << 8)
#define CHI_CHITXPTRA1(a)		(((a) << 8) & CHI_CHITXPTRA1MASK)
#define	CHI_CHITXPTRA0MASK		0xf
#define CHI_CHITXPTRA0(a)		((a) & CHI_CHITXPTRA0MASK)

#define OFF_CHI_TXPTRB			0x1ec
#define	CHI_CHITXPTRB3MASK		(0xf << 24)
#define CHI_CHITXPTRB3(a)		(((a) << 24) & CHI_CHITXPTRB3MASK)
#define	CHI_CHITXPTRB2MASK		(0xf << 16)
#define CHI_CHITXPTRB2(a)		(((a) << 16) & CHI_CHITXPTRB2MASK)
#define	CHI_CHITXPTRB1MASK		(0xf << 8)
#define CHI_CHITXPTRB1(a)		(((a) << 8) & CHI_CHITXPTRB1MASK)
#define	CHI_CHITXPTRB0MASK		0xf
#define CHI_CHITXPTRB0(a)		((a) & CHI_CHITXPTRB0MASK)

#define OFF_CHI_SIZE			0x1f0
#define CHI_CHIDMAPTRMASK		0x3ffc0000
#define CHI_CHIDMAPTR(a)		(((a) << 18) & CHI_CHIDMAPTR)
#define CHI_CHIBUFF1TIME		(1 << 15)
#define CHI_CHIMALOOP			(1 << 14)
#define CHI_CHISIZEMASK			0x3ffc
#define CHI_CHISIZE(a)			(((a) << 2) & CHI_HISIZEMASK
#define CHI_ENDMARXCHI			(1 <<2)
#define CHI_ENDMATXCHI			1

#define	OFF_CHIRXSTART			0x1f4
#define	CHI_RXSTARTMASK			0xfffffffc

#define	OFF_CHITXSTART			0x1f8
#define	CHI_TXSTARTMASK			0xfffffffc

#define OFF_CHITXHOLD			0x1fc
#define OFF_CHIRXHOLD			0x1fc

/*
   R3912 Interrupt Register
 */
#define OFF_INTR_STATUS1		0x100
#define INTR_LCDINT			(1 << 31)
#define INTR_DFINT			(1 << 30)
#define INTR_CHI0_5INT			(1 << 29)
#define INTR_CHI1_0INT			(1 << 28)
#define INTR_CHIDMACNTINT		(1 << 27)
#define INTR_CHIININTA			(1 << 26)
#define INTR_CHIININTB			(1 << 25)
#define INTR_CHIACTINT			(1 << 24)
#define INTR_CHIERRINT			(1 << 23)
#define INTR_SND0_5INT			(1 << 22)
#define INTR_SND1_0TINT			(1 << 21)
#define INTR_TEL0_5INT			(1 << 20)
#define INTR_TEL1_0TINT			(1 << 19)
#define INTR_SNDDMACNTINT		(1 << 18)
#define INTR_TELDMACNTINT		(1 << 17)
#define INTR_LSNDCLIPINT		(1 << 16)
#define INTR_RSNDCLIPINT		(1 << 15)
#define INTR_VALSNDPOSINT		(1 << 14)
#define INTR_VALSNDNEGINT		(1 << 13)
#define INTR_VALTELPOSINT		(1 << 12)
#define INTR_VALTELNEGINT		(1 << 11)
#define INTR_SNDININT			(1 << 10)
#define INTR_TELININT			(1 << 9)
#define INTR_SIBSF0INT			(1 << 8)
#define INTR_SIBSF1INT			(1 << 7)
#define INTR_SIBIRQPOSINT		(1 << 6)
#define INTR_SIBIRQNEGINT		(1 << 5)

#define OFF_INTR_STATUS2		0x104
#define INTR_UARTARXINT			(1 << 31)
#define INTR_UARTARXOVERRUNINT		(1 << 30)
#define INTR_UARTAFRAMEERRINT		(1 << 29)
#define INTR_UARTABREAKINT		(1 << 28)
#define INTR_UARTAPARITYERRINT		(1 << 27)
#define INTR_UARTATXINT			(1 << 26)
#define INTR_UARTATXOVERRUNINT		(1 << 25)
#define INTR_UARTAEMPTYINT		(1 << 24)
#define INTR_UARTADMAFULLINT		(1 << 23)
#define INTR_UARTADMAHALFINT		(1 << 22)
#define INTR_UARTBRXINT			(1 << 21)
#define INTR_UARTBRXOVERRUNINT		(1 << 20)
#define INTR_UARTBFRAMEERRINT		(1 << 19)
#define INTR_UARTBBREAKINT		(1 << 18)
#define INTR_UARTBPARITYERRINT		(1 << 17)
#define INTR_UARTBTXINT			(1 << 16)
#define INTR_UARTBTXOVERRUNINT		(1 << 15)
#define INTR_UARTBEMPTYINT		(1 << 14)
#define INTR_UARTBDMAFULLINT		(1 << 13)
#define INTR_UARTBDMAHALFINT		(1 << 12)
#define INTR_MBUSTXBUFAVAILINT		(1 << 11)
#define INTR_MBUSTXERRINT		(1 << 10)
#define INTR_MBUSEMPTYINT		(1 << 9)
#define INTR_MBUSRXBUFAVAILINT		(1 << 8)
#define INTR_MBUSRXERRINT		(1 << 7)
#define INTR_MBUSDETINT			(1 << 6)
#define INTR_MBUSDMAFULLINT		(1 << 5)
#define INTR_MBUSDMAHALFINT		(1 << 4)
#define INTR_MBUSPOSINT			(1 << 3)
#define INTR_MBUSNEGINT			(1 << 2)

#define OFF_INTR_STATUS3		0x108
#define INTR_MFIOPOSINT(a)		(1 << (a))

#define OFF_INTR_STATUS4		0x10c
#define INTR_MFIONEGINT(a)		(1 << (a))

#define OFF_INTR_STATUS5		0x110
#define INTR_RTCINT			(1 << 31)
#define INTR_ALARMINT			(1 << 30)
#define INTR_PREINT			(1 << 29)
#define INTR_STPTIMERINT		(1 << 28)
#define INTR_POSPWRINT			(1 << 27)		
#define INTR_NEGPWRINT			(1 << 26)		
#define INTR_POSPWROKINT		(1 << 25)		
#define INTR_NEGPWROKINT		(1 << 24)		
#define INTR_POSONBUTNINT		(1 << 23)		
#define INTR_NEGONBUTNINT		(1 << 22)		
#define INTR_SPIBUFAVAILINT		(1 << 21)
#define INTR_SPIERRINT			(1 << 20)
#define INTR_SPIRCVINT			(1 << 19)
#define INTR_SPIEMPTYINT		(1 << 18)
#define INTR_IRCONSMINT			(1 << 17)
#define INTR_CARSTINT			(1 << 16)
#define INTR_POSCARINT			(1 << 15)
#define INTR_NEGCARINT			(1 << 14)
#define INTR_IOPOSINT(a)		(1 << ((a) + 7))
#define INTR_IONEGINT(a)		(1 << (a))

#define OFF_INTR_STATUS6		0x114
#define INTR_IRQHIGH			(1 << 31)
#define INTR_IRQLOW			(1 << 30)
#define INTR_INTVECTMASK		0x0000003c
#define INTR_INTVECT(a)			(((a) << 2) & INTR_INTVECTMASK)
#define INTR_INTPRIO(status6)		((status6 & INTR_INTVECTMASK) >> 2)