p2.h

WINDOWS CE BSP用于SBC2440开发板

// Make sure this matches entry in config.bib
// These buffs are now offset via a constant
#define TOUCHPANEL_PENSAMPLES_BASE     (DMA_BUFFER_BASE + 0x00020000) 
#define TOUCHPANEL_PENSAMPLES_PHYS     (DMA_PHYSICAL_BASE + 0x00020000) 
#define AUDIO_DMA_BUFFER_BASE			  (DMA_BUFFER_BASE + 0x00002000)
#define AUDIO_DMA_BUFFER_PHYS			  (DMA_PHYSICAL_BASE + 0x00002000)

#define AUDIO_DMA_REG_BASE		(CPU_BASE + \
					(TOUCH_SOUND_SLOT * 2 * 0x10000))
#define IO_RECORD_PTR_LOW		(AUDIO_DMA_REG_BASE + 0x0010)
#define IO_RECORD_PTR_HIGH		(AUDIO_DMA_REG_BASE + 0x0014)
#define IO_PLAYBACK_PTR_LOW		(AUDIO_DMA_REG_BASE + 0x10010)
#define IO_PLAYBACK_PTR_HIGH		(AUDIO_DMA_REG_BASE + 0x10014)
*/

// 
// The following defs were only defined in the kernel\hal\shx\fwp2.src file for the SH3
// need to sync the tchaud.h and reg.h files in the
// touch screen and audio driver dirs.
//
#define soundIntrMask			0x0002		// mask for all 4 sound interrupts
#define playbackIntr			0x2000
#define playbackEndIntr			0x1000
#define recordIntr				0x8000
#define recordEndIntr			0x4000
#define soundIntr				playbackIntr | playbackEndIntr | recordIntr | recordEndIntr

// Touch panel sample area
//
// Note: It's important that buffer A and B are contiguous in memory and
//       16 bytes apart.

#define tchBufA				0x0000		// Sample buffer A
#define tchBufB				0x0010		// Sample buffer B
#define tchHalPointer		0x0020		// HAL's sample pointer
#define tchDevDrvPointer	0x0024		// Device driver's sample pointer
#define tchSemaphore		0x0028		// Touch/Audio sync semaphore
#define tchStatus			0x002c		// Status used for passing info from HAL to touch driver
#define tchCoordCount		0x0030 		// Coordinate count - used in touch HAL code
#define tchTimerState		0x0034		// Used for the timer handler state machine.

// Touch panel bit masks
#define ucbIntr				0x0008
#define ucbIntrMask			0x0008
#define penTimingIntr		0x0004
#define penTimingIntrMask	0x0004
#define penIntr				0x0010
#define penIntrMask			0x0010
#define regIntr				0x0001
#define regIntrMask			0x0001
#define penState			0x1000
#define penTimingEn			0x0400

// Touch panel status register value
#define TOUCH_PEN_DOWN		 0
#define TOUCH_PEN_UP		 1
#define TOUCH_PEN_SAMPLE 	 2

// Timer state machine values
#define TCH_DO_BIAS		 	0
#define TCH_DO_SAMPLE		1

#ifdef TOUCH_AUDIO_UCB1100
#define TOUCH_SAMPLE_VALID		 0x03ff		// Bits which are valid in a touch panel sample
#define TOUCH_MAX_COORD			 12			// Max coord count = max coords * 2 = 6 * 2 = 12
#endif //TOUCH_AUDIO_UCB1100

#ifdef  TOUCH_AUDIO_CRYSTAL
#define TOUCH_SAMPLE_VALID		 0x0fff		// Bits which are valid in a touch panel sample
#define TOUCH_MAX_COORD		 	16			// Max coord count = max coords * 2 = 8 * 2 = 16
#endif //TOUCH_AUDIO_CRYSTAL

#define TOUCH_CHG_BUF_MASK		 0x10		// Mask XOR'd with a buf address to get other buf address
#define TOUCH_X_REQ			 0x4400		// Request an X coordinate
									// This enables doSample, sets adcSel to 00 = get an X coord
									// and leaves the timer enabled
#define TOUCH_Y_REQ			 0x4c00		// Request a Y coordinate
									// This enables doSample, sets adcSel to 01 = get a Y coord
									// and leaves the timer enabled



/*
 * PCMCIA defines
 */

/*
 * PCMCIA Control register
 */
#define PCMCIA_ENABLE			0x40
#define PCMCIA_RESET			0x20
#define PCMCIA_INTR_MASK		0x10
#define PCMCIA_STATE_INTR_MASK	0x08
#define PCMCIA_MEM_WINDOW		0x07

/*
 * PCMCIA Interrupt register
 */
#define PCMCIA_WP			0x10
#define PCMCIA_CD2			0x08
#define PCMCIA_CD1			0x04
#define PCMCIA_INTR			0x02
#define PCMCIA_STATE_INTR		0x01

/*
 * PCMCIA Status register
 */
#define PCMCIA0_BVD1			0x8000
#define PCMCIA0_BVD2			0x4000
#define PCMCIA1_BVD1			0x2000
#define PCMCIA1_BVD2			0x1000
#define PCMCIA0_VSW1			0x0800
#define PCMCIA1_VSW1			0x0400
#define PCMCIA0_VSW2			0x0200
#define PCMCIA1_VSW2			0x0100

/*
 * PCMCIA Register addresses
 */
#define PCMCIA_REG0			    0x10	
#define PCMCIA_INTR_REG0		0x14	
#define PCMCIA_REG1			    0x18	
#define PCMCIA_INTR_REG1		0x1C	

#define PCMCIA_STATUS_REG		0x00	// Offset from PCMCIA_STATUS_BASE		
#define PCMCIA_CTL_REG			0x00    // Offset from PCMCIA_STATUS_BASE	


/*
 * CPU specific PCMCIA defines
 */


//
// ARM920 PCMCIA config  (PCMCIA currently not supported on ARM920)
// This is just a cut and paste of ARM720 Caveat Emptor!!!
//
//#ifdef ARM920
#define PCMCIA_BASE			    (SYSTEM_ASIC_REGS_BASE + 0x400)
#define PCMCIA_STATUS_BASE		(SYSTEM_ASIC_REGS_BASE + 0x02000000)

#define PCMCIA_MAPPED_SYSTEM_WINDOW_SIZE 0x800000	// Only 8 Mbyte mapped in system address space
//#define PCMCIA_NUM_WINDOWS     		10	
#define PCMCIA_NUM_WINDOWS     		5	
/*
#define PCMCIA0_8_ATTR_WIN_BASE 	0xa8000000
//#define PCMCIA1_8_ATTR_WIN_BASE 	0x2A000000
#define PCMCIA0_16_ATTR_WIN_BASE 	0xa8000000
//#define PCMCIA1_16_ATTR_WIN_BASE 	0x2A000000
#define PCMCIA_ATTR_WIN_SIZE    	0x00800000		// 8 MB

#define PCMCIA0_8_CMN_WIN_BASE  	0xac000000
//#define PCMCIA1_8_CMN_WIN_BASE  	0x2E000000
#define PCMCIA0_16_CMN_WIN_BASE  	0xac000000
//#define PCMCIA1_16_CMN_WIN_BASE  	0x2E000000
#define PCMCIA_CMN_WIN_SIZE     	0x00800000  		// 8 MB

#define PCMCIA0_8_IO_WIN_BASE     	0x30000000
//#define PCMCIA1_8_IO_WIN_BASE     	0x32000000

#define PCMCIA_IO_WIN_SIZE      	0x00200000  		// 2 MB
*/
/*
#define PCMCIA0_8_ATTR_WIN_BASE 	0x04000000
//#define PCMCIA1_8_ATTR_WIN_BASE 	0x04400000
#define PCMCIA0_16_ATTR_WIN_BASE 	0x04000000
//#define PCMCIA1_16_ATTR_WIN_BASE 	0x04400000
#define PCMCIA_ATTR_WIN_SIZE    	0x00800000		// 8 MB

#define PCMCIA0_8_CMN_WIN_BASE  	0x04800000
//#define PCMCIA1_8_CMN_WIN_BASE  	0x04c00000
#define PCMCIA0_16_CMN_WIN_BASE  	0x04800000
//#define PCMCIA1_16_CMN_WIN_BASE  	0x04c00000
#define PCMCIA_CMN_WIN_SIZE     	0x00800000  		// 8 MB

#define PCMCIA0_8_IO_WIN_BASE     	0x05000000
//#define PCMCIA1_8_IO_WIN_BASE     	0x05200000

#define PCMCIA_IO_WIN_SIZE      	0x00200000  		// 2 MB
*/

#define PCMCIA0_8_ATTR_WIN_BASE 	0xA4000000
//#define PCMCIA1_8_ATTR_WIN_BASE 	0xA4000000
#define PCMCIA0_16_ATTR_WIN_BASE 	0xA4000000
//#define PCMCIA1_16_ATTR_WIN_BASE 	0xA4000000
#define PCMCIA_ATTR_WIN_SIZE    	0x00400000		// 8 MB

#define PCMCIA0_8_CMN_WIN_BASE  	0xA4000000
//#define PCMCIA1_8_CMN_WIN_BASE  	0xA4800000
#define PCMCIA0_16_CMN_WIN_BASE  	0xA4000000
//#define PCMCIA1_16_CMN_WIN_BASE  	0xA4800000
#define PCMCIA_CMN_WIN_SIZE     	0x00400000  		// 8 MB

#define PCMCIA0_8_IO_WIN_BASE     	0xA5000000
//#define PCMCIA1_8_IO_WIN_BASE     	0xA5800000

#define PCMCIA_IO_WIN_SIZE      	0x00200000  		// 2 MB

//#endif // ARM920

/*
 *  Bus State Controller Defines
 */

#define BCN_BCR1		0xFFFFFF60
#define BCN_BCR2		0xFFFFFF62

#define BCN_BCR1_DRAM_A2N3D	0x0010	// Area 2 normal, Area 3 DRAM
#define BCN_BCR1_A5PCM		0x0002	// Area 5 is PCMCIA access		
#define BCN_BCR1_A6PCM		0x0001	// Area 6 is PCMCIA access		

#define BCN_BCR2_A6SZ_16 	0x2000 
#define BCN_BCR2_A5SZ_8 	0x0400
#define BCN_BCR2_A4SZ_32	0x0300 
#define BCN_BCR2_A3SZ_32 	0x00C0
#define BCN_BCR2_A2SZ_32  	0x0030
#define BCN_BCR2_A2SZ_16  	0x0020  // Reserved Area on SH3, 16-bit bus
#define BCN_BCR2_A1SZ_32	0x000C

/*
 * Defines for SMC ethernet board. 
 */
#define ETHERNET_BASE  (SYSTEM_ASIC_REGS_BASE + 0x3000)

// The low bit of this word is stored in the FPGA. If set to a 1, it will assert
// the RESET pin of the 91C94.
#define SMC_HARD_RESET_REG (ETHERNET_BASE + 32)
    
// For debug ethernet routines, we set aside a chunk of memory for packet buffers
// if the IMGEBOOT variable is set (see config.bib).
#define NOCACHE_BIT  0x20000000
#define EDBG_PHYSICAL_MEMORY_START ((DMA_BUFFER_BASE&~NOCACHE_BIT)+0x30000)

#endif // _P2_H_