clkcon.h

WINDOWS CE BSP用于SBC2440开发板

#ifndef _CLOCK_REG_H_
#define _CLOCK_REG_H_

#include "bitfield.h"

//
// CLOCK CONTROL REGISTER (CLKCON)
//

#define CLKCON_SPI		(KBit18)	// Control PCLK into SPI block (0=Disable,1=Enable)
#define CLKCON_IIS		(KBit17)	// Control PCLK into IIS block (0=Disable,1=Enable)
#define CLKCON_IIC		(KBit16)	// Control PCLK into IIC block (0=Disable,1=Enable)
#define CLKCON_ADC		(KBit15)	// Control PCLK into ADC block (0=Disable,1=Enable)
#define CLKCON_RTC		(KBit14)	// Control PCLK into RTC control block (0=Disable,1=Enable)
#define CLKCON_GPIO		(KBit13)	// Control PCLK into GPIO block (0=Disable,1=Enable)
#define CLKCON_UART2	(KBit12)	// Control PCLK into UART2 block (0=Disable,1=Enable)
#define CLKCON_UART1	(KBit11)	// Control PCLK into UART1 block (0=Disable,1=Enable)
#define CLKCON_UART0	(KBit10)	// Control PCLK into UART0 block (0=Disable,1=Enable)
#define CLKCON_SDI		(KBit9)		// Control PCLK into SDI interface block (0=Disable,1=Enable)
#define CLKCON_PWMTIMER	(KBit8)		// Control PCLK into PWMTIMER block (0=Disable,1=Enable)
#define CLKCON_USBD		(KBit7)		// Control PCLK into USB device block (0=Disable,1=Enable)
#define CLKCON_USBH		(KBit6)		// Control HCLK into USB host block (0=Disable,1=Enable)
#define CLKCON_LCDC		(KBit5)		// Control HCLK into LCDC block (0=Disable,1=Enable)
#define CLKCON_NFCON	(KBit4)		// Control HCLK into NAND Flash Controller block (0=Disable,1=Enable)
#define CLKCON_POWEROFF	(KBit3)		// Control Power Off mode of S3C2440 (0=Disable,1=Transition to Power_OFF mode)
#define CLKCON_IDLE_BIT	(KBit2)		// Enter IDLE Mode (0=Disable,1=Transition to IDLE mode)
#define CLKCON_RESERVED (KBit1)		// Reserved
#define CLKCON_SM_BIT	(KBit0)		// SPECIAL Mode (0=Disable,1=Enable)


//
// CLOCK SLOW CONTROL (CLKSLOW) REGISTER
//

#define UCLK_ON		(KBit7)
#define MPLL_OFF	(KBit5)
#define SLOW_BIT	(KBit4)
#define SLOW_VAL	(KBit2|KBit1|KBit0)


//
// CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER
//

#define HDIVN		(KBit1)		// 0 : HCLK = FCLK, 1 : HCLK = FCLK/2
#define PDIVN		(KBit0)		// 0 : PCLK = HCLK, 1 : PCLK = HCLK/2

#endif // _CLOCK_REG_H_