ledtest.fit.rpt

开发FPGA的入门程序.是一个4个LED点亮程序

Fitter report for ledtest
Sat Apr 18 01:46:25 2009
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Fitter Summary                                                                     ;
+------------------------------------+-----------------------------------------------+
; Fitter Status                      ; Failed - Sat Apr 18 01:46:25 2009             ;
; Quartus II Version                 ; 7.2 Build 175 11/20/2007 SP 1 SJ Full Version ;
; Revision Name                      ; ledtest                                       ;
; Top-level Entity Name              ; ledtest                                       ;
; Family                             ; Cyclone II                                    ;
; Device                             ; EP2C5Q208C7                                   ;
; Timing Models                      ; Final                                         ;
; Total logic elements               ; 0                                             ;
;     Total combinational functions  ; 0                                             ;
;     Dedicated logic registers      ; 0                                             ;
; Total registers                    ; 0                                             ;
; Total pins                         ; 2                                             ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 0                                             ;
; Embedded Multiplier 9-bit elements ; 0                                             ;
; Total PLLs                         ; 0                                             ;
+------------------------------------+-----------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; EP2C5Q208C7                    ;                                ;
; Minimum Core Junction Temperature                                     ; 0                              ;                                ;
; Maximum Core Junction Temperature                                     ; 85                             ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+---------------------------------------------------------------+
; Fitter Device Options                                         ;
+----------------------------------------------+----------------+
; Option                                       ; Setting        ;
+----------------------------------------------+----------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off            ;
; Enable device-wide reset (DEV_CLRn)          ; Off            ;
; Enable device-wide output enable (DEV_OE)    ; Off            ;
; Enable INIT_DONE output                      ; Off            ;
; Configuration scheme                         ; Passive Serial ;
; Error detection CRC                          ; Off            ;
; nCEO                                         ; Unreserved     ;
; ASDO,nCSO                                    ; Unreserved     ;
; Reserve all unused pins                      ; Unreserved     ;
; Base pin-out file on sameframe device        ; Off            ;
+----------------------------------------------+----------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Apr 18 01:46:24 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ledtest -c ledtest
Warning: FLEXlm software error: Invalid (inconsistent) license key  The license-key and data for the feature do not match.  This usually happens when a license file has been altered Feature:       quartus License path:  D:\altera\license\license.DAT FLEXlm error:  -8,523 For further information, refer to the FLEXlm End User Manual, available at "www.macrovision.com".
Error: Current license file does not support the EP2C5Q208C7 device
Error: Quartus II Fitter was unsuccessful. 1 error, 1 warning
    Info: Allocated 133 megabytes of memory during processing
    Error: Processing ended: Sat Apr 18 01:46:26 2009
    Error: Elapsed time: 00:00:02