📄 ch5example6.mdl
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axes1 ""
axes2 ""
}
TimeRange "0.002"
YMin "-5~-4"
YMax "5~3"
DataFormat "StructureWithTime"
}
Block {
BlockType Scope
Name "Scope2"
Ports [2]
Position [645, 146, 675, 179]
Location [475, 490, 799, 729]
Open on
NumInputPorts "2"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
List {
ListType SelectedSignals
axes1 ""
axes2 ""
}
TimeRange "0.002"
YMin "-6~-4"
YMax "5~3"
SaveName "ScopeData1"
DataFormat "StructureWithTime"
}
Block {
BlockType SignalGenerator
Name "Signal\nGenerator"
Position [20, 70, 50, 100]
Amplitude "5"
Frequency "1000"
Port {
PortNumber 1
Name "L(t)"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType SignalGenerator
Name "Signal\nGenerator3"
Position [20, 145, 50, 175]
Amplitude "2"
Frequency "2000"
Port {
PortNumber 1
Name "R(t)"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Reference
Name "Slider\nGain"
Ports [1, 1]
Position [315, 270, 345, 300]
SourceBlock "simulink/Math\nOperations/Slider\nGain"
SourceType "Slider Gain"
low "0"
gain "0.5"
high "2"
}
Block {
BlockType SubSystem
Name "SteroGen"
Ports [2, 1]
Position [95, 116, 150, 174]
TreatAsAtomicUnit off
System {
Name "SteroGen"
Location [471, 85, 871, 306]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [25, 40, 55, 54]
Port {
PortNumber 1
Name "L(t)"
PropagatedSignals "L(t)"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Inport
Name "In2"
Position [40, 180, 70, 194]
Port "2"
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [200, 36, 245, 69]
InputSameDT off
}
Block {
BlockType SignalGenerator
Name "Signal\nGenerator1"
Position [120, 75, 150, 105]
Frequency "38e3"
Port {
PortNumber 1
Name "38KHz"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType SignalGenerator
Name "Signal\nGenerator2"
Position [200, 115, 230, 145]
Frequency "19e3"
Port {
PortNumber 1
Name "19KHz导频"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [115, 150, 140, 190]
ShowName off
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [115, 25, 140, 65]
ShowName off
Inputs "|+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum2"
Ports [3, 1]
Position [295, 27, 320, 193]
ShowName off
Inputs "|+++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Outport
Name "Out1"
Position [345, 105, 375, 119]
}
Line {
Name "L(t)"
Labels [2, 0]
SrcBlock "In1"
SrcPort 1
Points [0, 0; 15, 0]
Branch {
DstBlock "Sum1"
DstPort 1
}
Branch {
Points [0, 125]
DstBlock "Sum"
DstPort 1
}
}
Line {
SrcBlock "In2"
SrcPort 1
Points [0, 0; 15, 0]
Branch {
Points [0, -125]
DstBlock "Sum1"
DstPort 2
}
Branch {
DstBlock "Sum"
DstPort 2
}
}
Line {
SrcBlock "Sum1"
SrcPort 1
DstBlock "Product"
DstPort 1
}
Line {
Name "38KHz"
Labels [2, 0]
SrcBlock "Signal\nGenerator1"
SrcPort 1
Points [0, -30]
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "Product"
SrcPort 1
Points [30, 0]
DstBlock "Sum2"
DstPort 1
}
Line {
Name "19KHz导频"
Labels [1, 1]
SrcBlock "Signal\nGenerator2"
SrcPort 1
DstBlock "Sum2"
DstPort 2
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "Sum2"
DstPort 3
}
Line {
SrcBlock "Sum2"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [585, 38, 605, 82]
ShowName off
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
Port {
PortNumber 1
Name "接收L(t)"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Sum
Name "Sum2"
Ports [2, 1]
Position [590, 248, 610, 292]
ShowName off
Inputs "|-+"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
Port {
PortNumber 1
Name "接收R(t)"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Reference
Name "Voltage-Controlled\nOscillator"
Ports [1, 1]
Position [410, 187, 460, 233]
Orientation "left"
FontName "Arial"
FontSize 10
SourceBlock "commcontsrc2/Voltage-Controlled\nOscillator"
SourceType "Voltage-Controlled Oscillator"
Ac "1"
Fc "38e3+20"
Kc "500"
Ph "0"
}
Line {
Name "L(t)"
SrcBlock "Signal\nGenerator"
SrcPort 1
Points [25, 0; 0, 45]
Branch {
DstBlock "SteroGen"
DstPort 1
}
Branch {
Points [0, 105]
DstBlock "Scope1"
DstPort 1
}
}
Line {
Name "R(t)"
SrcBlock "Signal\nGenerator3"
SrcPort 1
Points [0, 0; 15, 0]
Branch {
DstBlock "SteroGen"
DstPort 2
}
Branch {
Points [0, 90]
DstBlock "Scope1"
DstPort 2
}
}
Line {
SrcBlock "SteroGen"
SrcPort 1
Points [0, 0; 5, 0]
Branch {
DstBlock "Analog\nFilter Design1"
DstPort 1
}
Branch {
DstBlock "Analog\nFilter Design2"
DstPort 1
}
Branch {
DstBlock "Analog\nFilter Design"
DstPort 1
}
}
Line {
SrcBlock "Counter"
SrcPort 1
DstBlock "Analog\nFilter Design3"
DstPort 1
}
Line {
SrcBlock "Product"
SrcPort 1
Points [90, 0]
DstBlock "Voltage-Controlled\nOscillator"
DstPort 1
}
Line {
SrcBlock "Voltage-Controlled\nOscillator"
SrcPort 1
Points [0, 0; -10, 0]
Branch {
DstBlock "Counter"
DstPort 1
}
Branch {
DstBlock "Gain"
DstPort 1
}
}
Line {
SrcBlock "Analog\nFilter Design3"
SrcPort 1
Points [-5, 0; 0, -50]
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "Analog\nFilter Design2"
SrcPort 1
DstBlock "Product1"
DstPort 1
}
Line {
SrcBlock "Product1"
SrcPort 1
DstBlock "Analog\nFilter Design4"
DstPort 1
}
Line {
SrcBlock "Analog\nFilter Design"
SrcPort 1
DstBlock "Slider\nGain"
DstPort 1
}
Line {
SrcBlock "Analog\nFilter Design4"
SrcPort 1
Points [0, 0; 10, 0]
Branch {
DstBlock "Sum"
DstPort 1
}
Branch {
Points [0, 210]
DstBlock "Sum2"
DstPort 1
}
}
Line {
SrcBlock "Slider\nGain"
SrcPort 1
Points [0, 0; 220, 0]
Branch {
DstBlock "Sum"
DstPort 2
}
Branch {
DstBlock "Sum2"
DstPort 2
}
}
Line {
Name "接收L(t)"
Labels [2, 0]
SrcBlock "Sum"
SrcPort 1
Points [20, 0]
DstBlock "Scope2"
DstPort 1
}
Line {
Name "接收R(t)"
Labels [2, 0]
SrcBlock "Sum2"
SrcPort 1
Points [15, 0]
DstBlock "Scope2"
DstPort 2
}
Line {
SrcBlock "Gain"
SrcPort 1
Points [0, -25]
DstBlock "Product1"
DstPort 2
}
Line {
SrcBlock "Analog\nFilter Design1"
SrcPort 1
Points [25, 0; 0, -25]
DstBlock "Manual Switch"
DstPort 2
}
Line {
SrcBlock "Manual Switch"
SrcPort 1
Points [0, 35]
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Ground"
SrcPort 1
DstBlock "Manual Switch"
DstPort 1
}
Annotation {
Name "调频立体声解码测试模型\n文件名：ch5example6.mdl"
Position [307, 23]
DropShadow on
FontName "Arial"
FontSize 12
}
}
}
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