📄 l1_storage.c
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}
}
if (Dst == 0)
{
L2_SetDRAMDMA(dramaddr);
}
L2_CFSetMemA(0x00,0x00);
//richie@mi 0409 begin
//sss mark
//L2_DoDMA(2,Dst,SecSize,0,0);
//sss begin
if (Dst != K_DMA_USB)
{
// sync mode
if (Dst == 1)
{
L2_SetSRAMDMA(0x0C00);
}
error = L2_DoDMA(2,Dst,SecSize,0,0);
if (error != 0)
{
return FALSE;
}
}
else
{
UCHAR bi;
// async mode
error = L2_DoDMA(2,Dst,SecSize,1,0);
if (error != 0)
{
return FALSE;
}
for (bi=0;bi<8;bi++)
{
//patch4.5@richie@msdc plug out exception
while ((XBYTE[K_USB_CLASS_IN_BUF_SIZE] < 64) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait for 0 in bulk buffer
XBYTE[0x25a1] = K_USB_CLASS_IN_OPEN;//0x01;//open bulk in
//patch4.5@richie@msdc plug out exception
while (((XBYTE[0x25c2] & K_USB_CLASS_IN_ACK_MASK) == 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait pc ack
XBYTE[0x25c2] = XBYTE[0x25c2] & K_USB_CLASS_IN_ACK_RESET;//reset 0x25c2
}
}
//sss end
//richie@mi 0409 end
//check CF status register not busy and ready
Ready = 0x00;
while ((Ready & 0xc0) != 0x40)
{
error = L2_CFComMemRd(0x00,0x07,&Ready);
if (error != 0)
{
return FALSE;
}
}
if (Dst == 0)
{
dramaddr += (ULONG)(SecSize >> 1);
}
}
//patch4.5@ada@Add timeout count end
if ((CylLow == 255) && (CylHigh == 255))
{
Haddr++;
CylHigh = 0x00;
CylLow = 0x00;
}
else
{
if (CylLow == 255)
{
CylHigh++;
CylLow = 0x00;
}
else
{
CylLow++;
}
}
}
if (i != 0)
{
//patch4.5@ada@Add timeout count begin
//check CF status register not busy and ready
Ready = 0x00;
while ((Ready & 0xc0) != 0x40)
{
error = L2_CFComMemRd(0x00,0x07,&Ready);
if (error != 0)
{
return FALSE;
}
}
if (i == 256)
{
Scnt = 0;
}
else
{
Scnt = (UCHAR)i;
}
// Write command
error = L2_CFComMemWr(0x00,0x02,Scnt); // SecCnt
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x03,SecNum); // SecNu
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x04,CylLow); // CylLow
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x05,CylHigh); // CylHigh
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x06,Haddr); // Logical addrss
if (error != 0)
{
return FALSE;
}
// Write Sector command
error = L2_CFComMemWr(0x00,0x07,0x21);
if (error != 0)
{
return FALSE;
}
// DMA
for (tmp = 0; tmp < i; tmp++)
{
Ready = 0x00;
while (Ready != 0x58)
{
error = L2_CFComMemRd(0x00,0x07,&Ready);
if (error != 0)
{
return FALSE;
}
}
if (Dst == 0)
{
L2_SetDRAMDMA(dramaddr);
}
L2_CFSetMemA(0x00,0x00);
//richie@mi 0409 begin
//sss mark
//L2_DoDMA(2,Dst,SecSize,0,0);
//sss begin
if (Dst != K_DMA_USB)
{
// sync mode
if (Dst == 1)
{
L2_SetSRAMDMA(0x0C00);
}
error = L2_DoDMA(2,Dst,SecSize,0,0);
if (error != 0)
{
return FALSE;
}
}
else
{
UCHAR bi;
// async mode
error = L2_DoDMA(2,Dst,SecSize,1,0);
if (error != 0)
{
return FALSE;
}
for (bi=0;bi<8;bi++)
{
//patch4.5@richie@msdc plug out exception
while ((XBYTE[K_USB_CLASS_IN_BUF_SIZE] < 64) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait for 0 in bulk buffer
XBYTE[0x25a1] = K_USB_CLASS_IN_OPEN;//0x01;//open bulk in
//patch4.5@richie@msdc plug out exception
while (((XBYTE[0x25c2] & K_USB_CLASS_IN_ACK_MASK) == 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait pc ack
XBYTE[0x25c2] = XBYTE[0x25c2] & K_USB_CLASS_IN_ACK_RESET;//reset 0x25c2
}
}
//sss end
//richie@mi 0409 end
//check CF status register not busy and ready
Ready = 0x00;
while ((Ready & 0xc0) != 0x40)
{
error = L2_CFComMemRd(0x00,0x07,&Ready);
if (error != 0)
{
return FALSE;
}
}
if (Dst == 0)
{
dramaddr += (ULONG)(SecSize >> 1);
}
}
//patch4.5@ada@Add timeout count end
}
return TRUE;
}
/*
UCHAR L1_DMARdCFMEM(UCHAR Dst, UCHAR HS, UCHAR CylHigh, UCHAR CylLow, UCHAR SecNum, ULONG SecCnt, USHORT SecSize) USING_0
{
UCHAR Ready;
UCHAR Haddr;
USHORT tmp;
UCHAR Scnt;
ULONG dramaddr;
ULONG i;
//PRINT_L1(" L1_DMARdCFMEM: Enter L1_DMARdCFMEM(HS,CylHigh,CylLow,SecNum,SecCnt,SecSize)=(%x,%x,%x,%x,%lx,%x)\n",(USHORT)HS,(USHORT)CylHigh,(USHORT)CylLow,(USHORT)SecNum,SecCnt,(USHORT)SecSize);
L2_FlashMode(0x04, 0x01, 0x01);
if(Dst==0) L2_ReadDRAMDMAAdr(&dramaddr);
Haddr = 0xE0 | (HS&0x0F);
for(i = SecCnt; i>256 ; i=i-256)
{
Ready = 0;
while(!Ready) L2_CFCheckRdy(&Ready); // check interface ready
Ready = 0xff;
while((Ready&0x80)!=0) L2_CFComMemRd(0x00,0x07,&Ready); // check if busy
Ready = 0;
while((Ready&0x40)==0) L2_CFComMemRd(0x00,0x07,&Ready); // check if ready
// Write command
L2_CFComMemWr(0x00,0x06,Haddr); // Logical addrss
L2_CFComMemWr(0x00,0x02,0); // SecCnt
L2_CFComMemWr(0x00,0x03,SecNum); // SecNu
L2_CFComMemWr(0x00,0x04,CylLow); // CylLow
L2_CFComMemWr(0x00,0x05,CylHigh); // CylHigh
// Write command
// Write Sector command
L2_CFComMemWr(0x00,0x07,0x20);
// Write Sector command
// DMA
for(tmp = 0; tmp< 256 ; tmp++)
{
if(Dst == 0) L2_SetDRAMDMA(dramaddr);
Ready = 0;
while(!Ready) L2_CFCheckRdy(&Ready); // check interface ready
Ready = 0xff;
while((Ready&0x80)!=0) L2_CFComMemRd(0x00,0x07,&Ready); // check if busy
Ready = 0;
while((Ready&0x40)==0) L2_CFComMemRd(0x00,0x07,&Ready); // check if ready
if((Ready & 0x08)==0) return 0x02; // check if DRQ = 1
L2_CFSetMemA(0x00,0x00);
L2_DoDMA(2,Dst,SecSize,0,0);
L2_CFComMemRd(0x00,0x07,&Ready);
if((Ready & 0x01)!=0) return 0x03; // check if error occur
if(Dst == 0) dramaddr += (ULONG)(SecSize>>1);
}
if(CylLow==255 && CylHigh==255) Haddr++;
else if(CylLow==255) CylHigh++;
else CylLow++;
}
if(i != 0)
{
Ready = 0;
while(!Ready) L2_CFCheckRdy(&Ready); // check interface ready
Ready = 0xff;
while((Ready&0x80)!=0) L2_CFComMemRd(0x00,0x07,&Ready); // check if busy
Ready = 0;
while((Ready&0x40)==0) L2_CFComMemRd(0x00,0x07,&Ready); // check if ready
if(i==256) Scnt = 0;
else Scnt = (UCHAR)i;
// Write command
L2_CFComMemWr(0x00,0x06,Haddr); // Logical addrss
L2_CFComMemWr(0x00,0x02,Scnt); // SecCnt
L2_CFComMemWr(0x00,0x03,SecNum); // SecNu
L2_CFComMemWr(0x00,0x04,CylLow); // CylLow
L2_CFComMemWr(0x00,0x05,CylHigh); // CylHigh
// Write command
// Write Sector command
L2_CFComMemWr(0x00,0x07,0x20);
// Write Sector command
// DMA
for(tmp = 0; tmp< i ; tmp++)
{
if(Dst == 0) L2_SetDRAMDMA(dramaddr);
Ready = 0;
while(!Ready) L2_CFCheckRdy(&Ready); // check interface ready
Ready = 0xff;
while((Ready&0x80)!=0) L2_CFComMemRd(0x00,0x07,&Ready); // check if busy
Ready = 0;
while((Ready&0x40)==0) L2_CFComMemRd(0x00,0x07,&Ready); // check if ready
if((Ready & 0x08)==0) return 0x02; // check if DRQ = 1
L2_CFSetMemA(0x00,0x00);
L2_DoDMA(2,Dst,SecSize,0,0);
L2_CFComMemRd(0x00,0x07,&Ready);
if((Ready & 0x01)!=0) return 0x03; // check if error occur
if(Dst == 0) dramaddr += (ULONG)(SecSize>>1);
}
}
//PRINT_L1(" L1_DMARdCFMEM: Exit L1_DMARdCFMEM\n");
}
*/
#endif
#if (SD)
//-----------------------------------------------------------------------------
//L1_SDIdentification
//-----------------------------------------------------------------------------
// input paremeters:
// BlockSize - data length of one block
// return value:
// 0x00 - No error
// 0x01 - CMD55 error
// 0x02 - ACMD41 error
// 0x03 - CMD2 error
// 0x04 - CMD3 error
// 0x05 - CMD9 error
// 0x06 - ACMD51 error
// 0x07 - CRC16 error
// 0x08 - time out error
UCHAR L1_SDIdentification(USHORT BlockSize) USING_0 //ada@0219
{
UCHAR CmdBuf[5];
UCHAR RspBuf[17];
UCHAR i,error;
UCHAR READ_BL_LEN;
USHORT BLOCK_LEN;
USHORT C_SIZE;
UCHAR C_SIZE_MULT;
USHORT MULT;
ULONG BLOCKNR;
//PRINT_L1("Enter Idnetification\n");
L2_FlashMode(5, 1, 1);
L2_SDInit();
L2_SDConfig(3,0); //375KHz,1 bit bus
L2_SDBlockSize(BlockSize);
for(i=0; i<100; i++)
{ // Tx 80 clock for power on sequence
L2_SDTxDummy();
}
CmdBuf[0] = 0x40;
CmdBuf[1] = 0x00;
CmdBuf[2] = 0x00;
CmdBuf[3] = 0x00;
CmdBuf[4] = 0x00;
//patch4.5@ada@Add timeout count begin
error = L2_SDTxCommand(CmdBuf); // Tx "CMD0"
if (error != 0)
{
return 8;
}
//patch4.5@ada@Add timeout count end
L2_SDTxDummy();
do{
CmdBuf[0] = 0x77;
CmdBuf[1] = 0x00;
CmdBuf[2] = 0x00;
CmdBuf[3] = 0x00;
CmdBuf[4] = 0x00;
//patch4.5@ada@Add timeout count begin
error = L2_SDTxCommand(CmdBuf); // TX "CMD55"
if (error != 0)
{
return 8;
}
//patch4.5@ada@Add timeout count end
error=L2_SDRxResponse(RspBuf,0);
if(error!=0) return 0x01;
if(RspBuf[0]!=0x37) return 0x01; // check the response number
CmdBuf[0] = 0x69;
CmdBuf[1] = 0x00;
CmdBuf[2] = 0x04;
CmdBuf[3] = 0x00;
CmdBuf[4] = 0x00;
//patch4.5@ada@Add timeout count begin
error = L2_SDTxCommand(CmdBuf); // TX "ACMD41"
if (error != 0)
{
return 8;
}
//patch4.5@ada@Add timeout count end
error=L2_SDRxResponse(RspBuf,0);
if(RspBuf[0]!=0x3f) return 0x02; // check the response number
} while((RspBuf[1] & 0x80)==0);
// get card's OCR register
// for(i=0; i<4; i++) SD_OCR[i] = RspBuf[i+1];
CmdBuf[0] = 0x42;
CmdBuf[1] = 0x00;
CmdBuf[2] = 0x00;
CmdBuf[3] = 0x00;
CmdBuf[4] = 0x00;
//patch4.5@ada@Add timeout count begin
error = L2_SDTxCommand(CmdBuf); // TX "CMD2"
if (error != 0)
{
return 8;
}
//patch4.5@ada@Add timeout count end
error=L2_SDRxResponse(RspBuf,1);
if(RspBuf[0]!=0x3f) return 0x03; // check if response number
// get card's CID register
for(i=0; i<16; i++) SD_CID[i] = RspBuf[i+1];
CmdBuf[0] = 0x43;
CmdBuf[1] = 0x00;
CmdBuf[2] = 0x00;
CmdBuf[3] = 0x00;
CmdBuf[4] = 0x00;
//patch4.5@ada@Add timeout count begin
error = L2_SDTxCommand(CmdBuf); // TX "CMD3"
if (error != 0)
{
return 8;
}
//patch4.5@ada@Add timeout count end
error=L2_SDRxResponse(RspBuf,0);
if(error!=0) return 0x04;
if(RspBuf[0]!=0x03) return 0x04; // check the response number
// get card's RCA register
SD_RCA[0]=RspBuf[1];
SD_RCA[1]=RspBuf[2];
CmdBuf[0] = 0x49;
CmdBuf[1] = SD_RCA[0];
CmdBuf[2] = SD_RCA[1];
CmdBuf[3] = 0x00;
CmdBuf[4] = 0x⌨️ 快捷键说明
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