📄 l1_storage.c
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return FALSE;
}
error = L2_CFComMemRd(0x00,0x07,&Ready);
}
if (Src == 0)
{
L2_SetDRAMDMA(dramaddr);
}
L2_CFSetMemA(0x00,0x00);
//richie@mi 0411 mark
//L2_DoDMA(Src,2,SecSize,0,0);
//richie@mi 0411 begin
if (Src != K_DMA_USB)
{
// sync mode
if (Src == 1)
{
L2_SetSRAMDMA(0x0C00);
}
error = L2_DoDMA(Src,2,SecSize,0,0);
if (error != 0)
{
return FALSE;
}
}
else
{
UCHAR bi;
// async mode
error = L2_DoDMA(Src,2,SecSize,1,0);
if (error != 0)
{
return FALSE;
}
for (bi=0;bi<8;bi++)
{
//patch4.5@richie@msdc plug out exception
while ((XBYTE[K_USB_CLASS_OUT_BUF_SIZE] > 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait for 0 in bulk buffer
XBYTE[0x25a1] = K_USB_CLASS_OUT_OPEN;//0x02;//open bulk out
//patch4.5@richie@msdc plug out exception
while (((XBYTE[0x25c2] & K_USB_CLASS_OUT_ACK_MASK) == 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait pc ack
XBYTE[0x25c2] = XBYTE[0x25c2] & K_USB_CLASS_OUT_ACK_RESET;//reset 0x25c2
}
//patch4.5@richie@msdc plug out exception
while ((XBYTE[K_USB_CLASS_OUT_BUF_SIZE] > 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait for 0 in bulk buffer
}
//richie@mi 0411 end
//check CF status register not busy and ready
Ready = 0x00;
while ((Ready & 0xc0) != 0x40)
{
error = L2_CFComMemRd(0x00,0x07,&Ready);
if (error != 0)
{
return FALSE;
}
}
if (Src == 0)
{
dramaddr += (ULONG)(SecSize >> 1);
}
}
//patch4.5@ada@Add timeout count end
if ((CylLow == 255) && (CylHigh == 255))
{
Haddr++;
CylHigh = 0x00;
CylLow = 0x00;
}
else
{
if (CylLow == 255)
{
CylHigh++;
CylLow = 0x00;
}
else
{
CylLow++;
}
}
}
if (i != 0)
{
//patch4.5@ada@Add timeout count begin
//check CF status register not busy and ready
Ready = 0x00;
while ((Ready & 0xc0) != 0x40)
{
error = L2_CFComMemRd(0x00,0x07,&Ready);
if (error != 0)
{
return FALSE;
}
}
if (i == 256)
{
Scnt = 0;
}
else
{
Scnt = (UCHAR)i;
}
// Write command
error = L2_CFComMemWr(0x00,0x02,Scnt); // SecCnt
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x03,SecNum); // SecNu
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x04,CylLow); // CylLow
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x05,CylHigh); // CylHigh
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x06,Haddr); // Logical addrss
if (error != 0)
{
return FALSE;
}
// Write Sector command
error = L2_CFComMemWr(0x00,0x07,0x31);
if (error != 0)
{
return FALSE;
}
// DMA
for (tmp = 0; tmp < i ; tmp++)
{
Ready = 0x00;
while (Ready != 0x58)
{
error = L2_CFComMemRd(0x00,0x07,&Ready);
if (error != 0)
{
return FALSE;
}
}
if (Src == 0)
{
L2_SetDRAMDMA(dramaddr);
}
L2_CFSetMemA(0x00,0x00);
//richie@mi 0411 mark
//L2_DoDMA(Src,2,SecSize,0,0);
//richie@mi 0411 begin
if (Src != K_DMA_USB)
{
// sync mode
if (Src == 1)
{
L2_SetSRAMDMA(0x0C00);
}
error = L2_DoDMA(Src,2,SecSize,0,0);
if (error != 0)
{
return FALSE;
}
}
else
{
UCHAR bi;
// async mode
error = L2_DoDMA(Src,2,SecSize,1,0);
if (error != 0)
{
return FALSE;
}
for (bi=0;bi<8;bi++)
{
//patch4.5@richie@msdc plug out exception
while ((XBYTE[K_USB_CLASS_OUT_BUF_SIZE] > 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait for 0 in bulk buffer
XBYTE[0x25a1] = K_USB_CLASS_OUT_OPEN;//0x02;//open bulk out
//patch4.5@richie@msdc plug out exception
while (((XBYTE[0x25c2] & K_USB_CLASS_OUT_ACK_MASK) == 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait pc ack
XBYTE[0x25c2] = XBYTE[0x25c2] & K_USB_CLASS_OUT_ACK_RESET;//reset 0x25c2
}
//patch4.5@richie@msdc plug out exception
while ((XBYTE[K_USB_CLASS_OUT_BUF_SIZE] > 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait for 0 in bulk buffer
}
//richie@mi 0411 end
//check CF status register not busy and ready
Ready = 0x00;
while ((Ready & 0xc0) != 0x40)
{
error = L2_CFComMemRd(0x00,0x07,&Ready);
if (error != 0)
{
return FALSE;
}
}
if (Src == 0)
{
dramaddr += (ULONG)(SecSize >> 1);
}
}
//check CF status register not busy and ready
Ready = 0x00;
while ((Ready & 0xc0) != 0x40)
{
error = L2_CFComMemRd(0x00,0x07,&Ready);
if (error != 0)
{
return FALSE;
}
}
//patch4.5@ada@Add timeout count end
}
return TRUE;
}
/*
UCHAR L1_DMAWrCFMEM(UCHAR Src, UCHAR HS, UCHAR CylHigh, UCHAR CylLow, UCHAR SecNum, ULONG SecCnt, USHORT SecSize) USING_0
{
UCHAR Ready;
UCHAR Haddr;
USHORT tmp;
UCHAR Scnt;
ULONG dramaddr;
ULONG i;
//PRINT_L1(" L1_DMAWrCFMEM: Enter L1_DMAWrCFMEM(HS,CylHigh,CylLow,SecNum,SecCnt,SecSize)=(%x,%x,%x,%x,%lx,%x)\n",(USHORT)HS,(USHORT)CylHigh,(USHORT)CylLow,(USHORT)SecNum,SecCnt,(USHORT)SecSize);
L2_FlashMode(0x04, 0x01, 0x01);
if(Src==0) L2_ReadDRAMDMAAdr(&dramaddr);
Haddr = 0xE0 | (HS&0x0F);
for(i = SecCnt; i>256 ; i=i-256)
{
Ready = 0;
while(!Ready) L2_CFCheckRdy(&Ready); // check interface ready
Ready = 0xff;
while((Ready&0x80)!=0) L2_CFComMemRd(0x00,0x07,&Ready); // check if busy
Ready = 0;
while((Ready&0x40)==0) L2_CFComMemRd(0x00,0x07,&Ready); // check if ready
// Write command
L2_CFComMemWr(0x00,0x06,Haddr); // Logical addrss
L2_CFComMemWr(0x00,0x02,0); // SecCnt
L2_CFComMemWr(0x00,0x03,SecNum); // SecNu
L2_CFComMemWr(0x00,0x04,CylLow); // CylLow
L2_CFComMemWr(0x00,0x05,CylHigh); // CylHigh
// Write command
// Write Sector command
L2_CFComMemWr(0x00,0x07,0x30);
// Write Sector command
// DMA
for(tmp = 0; tmp< 256 ; tmp++)
{
if(Src == 0) L2_SetDRAMDMA(dramaddr);
Ready = 0;
while(!Ready) L2_CFCheckRdy(&Ready); // check interface ready
Ready = 0xff;
while((Ready&0x80)!=0) L2_CFComMemRd(0x00,0x07,&Ready); // check if busy
Ready = 0;
while((Ready&0x40)==0) L2_CFComMemRd(0x00,0x07,&Ready); // check if ready
if((Ready & 0x08)==0) return 0x02; // check if DRQ = 1
L2_CFSetMemA(0x00,0x00);
L2_DoDMA(Src,2,SecSize,0,0);
L2_CFComMemRd(0x00,0x07,&Ready);
if((Ready & 0x01)!=0) return 0x03; // check if error occur
if(Src == 0) dramaddr += (ULONG)(SecSize>>1);
}
if(CylLow==255 && CylHigh==255) Haddr++;
else if(CylLow==255) CylHigh++;
else CylLow++;
}
if(i != 0)
{
Ready = 0;
while(!Ready) L2_CFCheckRdy(&Ready); // check interface ready
Ready = 0xff;
while((Ready&0x80)!=0) L2_CFComMemRd(0x00,0x07,&Ready); // check if busy
Ready = 0;
while((Ready&0x40)==0) L2_CFComMemRd(0x00,0x07,&Ready); // check if ready
if(i==256) Scnt = 0;
else Scnt = (UCHAR)i;
// Write command
L2_CFComMemWr(0x00,0x06,Haddr); // Logical addrss
L2_CFComMemWr(0x00,0x02,Scnt); // SecCnt
L2_CFComMemWr(0x00,0x03,SecNum); // SecNu
L2_CFComMemWr(0x00,0x04,CylLow); // CylLow
L2_CFComMemWr(0x00,0x05,CylHigh); // CylHigh
// Write command
// Write Sector command
L2_CFComMemWr(0x00,0x07,0x30);
// Write Sector command
// DMA
for(tmp = 0; tmp< i ; tmp++)
{
if(Src == 0) L2_SetDRAMDMA(dramaddr);
Ready = 0;
while(!Ready) L2_CFCheckRdy(&Ready); // check interface ready
Ready = 0xff;
while((Ready&0x80)!=0) L2_CFComMemRd(0x00,0x07,&Ready); // check if busy
Ready = 0;
while((Ready&0x40)==0) L2_CFComMemRd(0x00,0x07,&Ready); // check if ready
if((Ready & 0x08)==0) return 0x02; // check if DRQ = 1
L2_CFSetMemA(0x00,0x00);
L2_DoDMA(Src,2,SecSize,0,0);
L2_CFComMemRd(0x00,0x07,&Ready);
if((Ready & 0x01)!=0) return 0x03; // check if error occur
if(Src == 0) dramaddr += (ULONG)(SecSize>>1);
}
}
//PRINT_L1(" L1_DMAWrCFMEM: Exit L1_DMAWrCFMEM\n");
}
*/
//-----------------------------------------------------------------------------
//L1_DMARdCFMEM
//-----------------------------------------------------------------------------
/*
routine description:
DMA read data from CF card in memory mode
arguments:
Dst: the destination of DMA
0: DRAM
1: CPU 4K SRAM (0x1000 ~ 0x1FFF)
2: forbidden (flash itself)
3: Audio
4: USB
5: DMA data port (0x2300)
CylHigh: CF card register: cylinder high
CylLow: CF card register: cylinder low
SecNum: CF card register: sector number
SecSize: the number of byte in a sector
SecCnt: the number of sector
return value:
TRUE - success
FALSE - error
*/
//ada@0312
UCHAR L1_DMARdCFMEM(UCHAR Dst, UCHAR HS, UCHAR CylHigh, UCHAR CylLow, UCHAR SecNum, ULONG SecCnt, USHORT SecSize) USING_0
{
UCHAR Ready;
UCHAR Haddr;
UCHAR Scnt;
USHORT tmp;
ULONG dramaddr;
ULONG i;
//patch4.5@ada@Add timeout count begin
USHORT timeout_count = 0xffff;
UCHAR error;
//patch4.5@ada@Add timeout count end
if (Dst == 0)
{
L2_ReadDRAMDMAAdr(&dramaddr);
}
// check interface ready
Ready = 0x00;
while ((Ready & 0x01) != 0x00)
{
//patch4.5@ada@Add timeout count begin
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
//patch4.5@ada@Add timeout count end
L2_CFCheckRdy(&Ready);
}
Haddr = 0xE0 | (HS & 0x0F);
for (i = SecCnt; i > 256 ; i = (i - 256))
{
//patch4.5@ada@Add timeout count begin
//check CF status register not busy and ready
Ready = 0x00;
while ((Ready & 0xc0) != 0x40)
{
error = L2_CFComMemRd(0x00,0x07,&Ready);
if (error != 0)
{
return FALSE;
}
}
// Write command
error = L2_CFComMemWr(0x00,0x02,0); // SecCnt
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x03,SecNum); // SecNu
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x04,CylLow); // CylLow
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x05,CylHigh); // CylHigh
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x06,Haddr); // Logical addrss
if (error != 0)
{
return FALSE;
}
// Write Sector command
error = L2_CFComMemWr(0x00,0x07,0x21);
if (error != 0)
{
return FALSE;
}
// DMA
for (tmp = 0; tmp < 256 ; tmp++)
{
Ready = 0x00;
while (Ready != 0x58)
{
error = L2_CFComMemRd(0x00,0x07,&Ready);
if (error != 0)
{
return FALSE;
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