📄 l1_storage.c
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if (Src == 0)
{
dramaddr += (ULONG)(SecSize >> 1);
}
}
}
return TRUE;
}
//-----------------------------------------------------------------------------
//L1_DMARdCFIDE
//-----------------------------------------------------------------------------
/*
routine description:
DMA read data from CF card in IDE mode
arguments:
Dst: the destination of DMA
0: DRAM
1: CPU 4K SRAM (0x1000 ~ 0x1FFF)
2: forbidden (flash itself)
3: Audio
4: USB
5: DMA data port (0x2300)
CylHigh: CF card register: cylinder high
CylLow: CF card register: cylinder low
SecNum: CF card register: sector number
SecSize: the number of byte in a sector
SecCnt: the number of sector
return value:
TRUE - success
FALSE - error
*/
//ada@0312
UCHAR L1_DMARdCFIDE(UCHAR Dst, UCHAR HS, UCHAR CylHigh, UCHAR CylLow, UCHAR SecNum, ULONG SecCnt, USHORT SecSize) USING_0
{
UCHAR Ready;
USHORT WordData;
UCHAR Haddr;
UCHAR Scnt;
USHORT tmp;
ULONG dramaddr;
ULONG i;
//patch4.5@ada@Add timeout count begin
USHORT timeout_count = 0xffff;
UCHAR error;
//patch4.5@ada@Add timeout count end
if (Dst == 0)
{
L2_ReadDRAMDMAAdr(&dramaddr);
}
// check interface ready
Ready = 0x00;
while ((Ready & 0x01) != 0x00)
{
//patch4.5@ada@Add timeout count begin
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
//patch4.5@ada@Add timeout count end
L2_CFCheckRdy(&Ready);
}
Haddr = 0xE0 | (HS & 0x0F);
for (i = SecCnt; i > 256 ; i = (i - 256))
{
//check CF status register not busy and ready
//patch4.5@ada@Add timeout count begin
timeout_count = 0xffff;
WordData = 0x0000;
while ((WordData & 0x00c0) != 0x0040)
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
L2_CFSetWordCsARd(0x17,&WordData);
}
//patch4.5@ada@Add timeout count end
// Write command
L2_CFSetWordCsAWr(0x12,0x0000); // Sec Cnt
L2_CFSetWordCsAWr(0x13,(USHORT)SecNum); // Sec Nu.
L2_CFSetWordCsAWr(0x14,(USHORT)CylLow); // CylLow
L2_CFSetWordCsAWr(0x15,(USHORT)CylHigh); // CylHigh
L2_CFSetWordCsAWr(0x16,(USHORT)Haddr); //ada@0312
// Write Sector command
L2_CFSetWordCsAWr(0x17,0x0021);
// DMA
for (tmp = 0; tmp < 256 ; tmp++)
{
// check if busy
//patch4.5@ada@Add timeout count begin
timeout_count = 0xffff;
WordData = 0x0000;
while (WordData != 0x0058)
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
L2_CFSetWordCsARd(0x17,&WordData);
}
//patch4.5@ada@Add timeout count end
if (Dst == 0)
{
L2_SetDRAMDMA(dramaddr);
}
L2_CFSetCsA(0x10);
//richie@mi 0409 begin
//sss mark
//L2_DoDMA(2,Dst,SecSize,0,0);
//sss begin
if (Dst != K_DMA_USB)
{
//sync mode
//patch4.5@ada@Add timeout count begin
if (Dst == 1)
{
L2_SetSRAMDMA(0x0C00);
}
error = L2_DoDMA(2,Dst,SecSize,0,0);
if (error != 0)
{
return FALSE;
}
//patch4.5@ada@Add timeout count end
}
else
{
UCHAR bi;
// async mode
//patch4.5@ada@Add timeout count begin
error = L2_DoDMA(2,Dst,SecSize,1,0);
if (error != 0)
{
return FALSE;
}
//patch4.5@ada@Add timeout count end
for (bi=0;bi<8;bi++)
{
//patch4.5@richie@msdc plug out exception
while ((XBYTE[K_USB_CLASS_IN_BUF_SIZE] < 64) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait for 0 in bulk buffer
XBYTE[0x25a1] = K_USB_CLASS_IN_OPEN;//0x01;//open bulk in
//patch4.5@richie@msdc plug out exception
while (((XBYTE[0x25c2] & K_USB_CLASS_IN_ACK_MASK) == 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait pc ack
XBYTE[0x25c2] = XBYTE[0x25c2] & K_USB_CLASS_IN_ACK_RESET;//reset 0x25c2
}
}
//sss end
//richie@mi 0409 end
//ada@0312
//patch4.5@ada@Add timeout count begin
timeout_count = 0xffff;
WordData = 0x0000;
while ((WordData & 0x00c0) != 0x0040) //check CF status register not busy and ready
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
L2_CFSetWordCsARd(0x17,&WordData);
}
//patch4.5@ada@Add timeout count end
if (Dst == 0)
{
dramaddr += (ULONG)(SecSize >> 1);
}
}
if ((CylLow == 255) && (CylHigh == 255))
{
Haddr++;
CylHigh = 0x00;
CylLow = 0x00;
}
else
{
if (CylLow == 255)
{
CylHigh++;
CylLow = 0x00;
}
else
{
CylLow++;
}
}
}
if (i != 0)
{
// check if busy
//patch4.5@ada@Add timeout count begin
timeout_count = 0xffff;
WordData = 0x0000;
while ((WordData & 0xC0) != 0x40)
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
L2_CFSetWordCsARd(0x17,&WordData);
}
//patch4.5@ada@Add timeout count end
if (i == 256)
{
Scnt = 0;
}
else
{
Scnt = (UCHAR)i;
}
// Write command
L2_CFSetWordCsAWr(0x12,(USHORT)Scnt); // Sec Cnt
L2_CFSetWordCsAWr(0x13,(USHORT)SecNum); // Sec Nu.
L2_CFSetWordCsAWr(0x14,(USHORT)CylLow); // CylLow
L2_CFSetWordCsAWr(0x15,(USHORT)CylHigh); // CylHigh
L2_CFSetWordCsAWr(0x16,(USHORT)Haddr);
// Write Sector command
L2_CFSetWordCsAWr(0x17,0x0021);
// DMA
for (tmp = 0; tmp < i; tmp++)
{
// check if busy
//patch4.5@ada@Add timeout count begin
timeout_count = 0xffff;
WordData = 0x0000;
while (WordData != 0x0058)
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
L2_CFSetWordCsARd(0x17,&WordData);
}
//patch4.5@ada@Add timeout count end
if (Dst == 0)
{
L2_SetDRAMDMA(dramaddr);
}
L2_CFSetCsA(0x10);
//richie@mi 0409 begin
//sss mark
//L2_DoDMA(2,Dst,SecSize,0,0);
//sss begin
if (Dst != K_DMA_USB)
{
// sync mode
//patch4.5@ada@Add timeout count begin
if (Dst == 1)
{
L2_SetSRAMDMA(0x0C00);
}
error = L2_DoDMA(2,Dst,SecSize,0,0);
if (error != 0)
{
return FALSE;
}
//patch4.5@ada@Add timeout count end
}
else
{
UCHAR bi;
// async mode
//patch4.5@ada@Add timeout count begin
error = L2_DoDMA(2,Dst,SecSize,1,0);
if (error != 0)
{
return FALSE;
}
//patch4.5@ada@Add timeout count end
for (bi=0;bi<8;bi++)
{
//patch4.5@richie@msdc plug out exception
while ((XBYTE[K_USB_CLASS_IN_BUF_SIZE] < 64) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait for 0 in bulk buffer
XBYTE[0x25a1] = K_USB_CLASS_IN_OPEN;//0x01;//open bulk in
//patch4.5@richie@msdc plug out exception
while (((XBYTE[0x25c2] & K_USB_CLASS_IN_ACK_MASK) == 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait pc ack
XBYTE[0x25c2] = XBYTE[0x25c2] & K_USB_CLASS_IN_ACK_RESET;//reset 0x25c2
}
}
//sss end
//richie@mi 0409 end
//check CF status register not busy and ready
//patch4.5@ada@Add timeout count begin
timeout_count = 0xffff;
WordData = 0x0000;
while ((WordData & 0x00c0) != 0x0040)
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
L2_CFSetWordCsARd(0x17,&WordData);
}
//patch4.5@ada@Add timeout count end
if (Dst == 0)
{
dramaddr += (ULONG)(SecSize >> 1);
}
}
}
return TRUE;
}
#endif
#if (CFAMEM)
//-----------------------------------------------------------------------------
//L1_DMAWrCFMEM
//-----------------------------------------------------------------------------
/*
routine description:
DMA write data from CF card in memory mode
arguments:
Src: the source of DMA
0: DRAM
1: CPU 4K SRAM (0x1000 ~ 0x1FFF)
2: forbidden (flash itself)
3: Audio
4: USB
5: DMA data port (0x2300)
CylHigh: CF card register: cylinder high
CylLow: CF card register: cylinder low
SecNum: CF card register: sector number
SecSize: the number of byte in a sector
SecCnt: the number of sector
return value:
TRUE - success
FALSE - error
*/
//ada@0312
UCHAR L1_DMAWrCFMEM(UCHAR Src, UCHAR HS, UCHAR CylHigh, UCHAR CylLow, UCHAR SecNum, ULONG SecCnt, USHORT SecSize) USING_0
{
UCHAR Ready;
UCHAR Haddr;
UCHAR Scnt;
USHORT tmp;
ULONG dramaddr;
ULONG i;
//patch4.5@ada@Add timeout count begin
USHORT timeout_count = 0xffff;
UCHAR error = 0;
//patch4.5@ada@Add timeout count end
if (Src == 0)
{
L2_ReadDRAMDMAAdr(&dramaddr);
}
// check interface ready
Ready = 0x00;
while ((Ready & 0x01) != 0x00)
{
//patch4.5@ada@Add timeout count begin
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
//patch4.5@ada@Add timeout count end
L2_CFCheckRdy(&Ready);
}
Haddr = 0xE0 | (HS & 0x0F);
for (i = SecCnt; i > 256 ; i = (i - 256))
{
//check CF status register not busy and ready
//patch4.5@ada@Add timeout count begin
Ready = 0x00;
while ((Ready & 0xc0) != 0x40)
{
error = L2_CFComMemRd(0x00,0x07,&Ready);
if (error != 0)
{
return FALSE;
}
}
// Write command
error = L2_CFComMemWr(0x00,0x02,0); // SecCnt
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x03,SecNum); // SecNu
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x04,CylLow); // CylLow
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x05,CylHigh); // CylHigh
if (error != 0)
{
return FALSE;
}
error = L2_CFComMemWr(0x00,0x06,Haddr); // Logical addrss
if (error != 0)
{
return FALSE;
}
// Write Sector command
error = L2_CFComMemWr(0x00,0x07,0x31);
if (error != 0)
{
return FALSE;
}
// DMA
for (tmp = 0; tmp < 256; tmp++)
{
Ready = 0x00;
while (Ready != 0x58)
{
if (error != 0)
{
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