📄 l1_storage.c
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L2_NANDSendCmd(0x10);
//patch4.5@ada@Add timeout count begin
//Status = 0x01;
//while(Status!=0) L2_NANDCheckRdy(&Status);
L2_NANDCheckRdy(&error);
if (error != 0)
{
return error;
}
//patch4.5@ada@Add timeout count end
L2_NANDSendCmd(0x70);
L2_NANDReadPort(&Status);
L2_NANDCompleteOperation();
if(Status != 0xC0) {error = 1; return 0x02;}
if(Src == 0) dramaddr += (ULONG)(PageSize>>1);
Addr++;
}
//PRINT_L1(" L1_DMAWrNAND: Exit L1_DMAWrNAND(error = %x)\n",(USHORT)error);
return error;
}
//-----------------------------------------------------------------------------
//L1_DMARdNAND
//-----------------------------------------------------------------------------
/*
routine description:
DMA read data from nand gate flash
arguments:
Dst: the destination of DMA
0: DRAM
1: CPU 4K SRAM (0x1000 ~ 0x1FFF)
2: forbidden (flash itself)
3: Audio
4: USB
5: DMA data port (0x2300)
NandSize: the size of nand gate flash (in the unit of Mbytes)
example: NandSize = 8 , that is 8 M bytes nand gate flash
Addr: the start address of nand gate flash to be read from
PageCnt: the number of page to be transfer (0 is 256 pages)maximum page is 256
PageSize: the number of bytes in a page
return value:
0x00 - success
others - error
*/
UCHAR L1_DMARdNAND(UCHAR Dst, UCHAR NandSize, ULONG Addr, ULONG PageCnt, USHORT PageSize) USING_0
{
ULONG dramaddr;
ULONG tmp;
UCHAR tmp0;
UCHAR ECCCnt;
UCHAR LowAddr;
UCHAR ECCData[12];
UCHAR ByteData;
//patch4.5@ada@Add timeout count begin
UCHAR error;
//patch4.5@ada@Add timeout count end
//PRINT_L1(" L1_DMARdNAND: Enter L1_DMARdNAND(Dst,Addr,PageCnt,PageSize)=(%x,%lx,%lx,%x)\n",(USHORT)Dst,Addr,PageCnt,PageSize);
if(Dst==0) L2_ReadDRAMDMAAdr(&dramaddr);
LowAddr = (UCHAR)(Addr&0x000000ff);
for(tmp0 = 0; tmp0<12 ; tmp0++) ECCData[tmp0] = 0xff;
if(PageSize == 256) {Addr = Addr >> 8; ECCCnt = 3;}
else if(PageSize == 512) {Addr = Addr >> 9; ECCCnt = 6;}
else if(PageSize == 1024) {Addr = Addr >> 10; ECCCnt = 12;}
else return 0x01;
error = 0;
for(tmp = 0; tmp< PageCnt ; tmp++)
{
if(Dst == 0) L2_SetDRAMDMA(dramaddr);
L2_NANDSendCmd(0x00);
L2_NANDSendAddr(1,LowAddr);
if(NandSize < 16)
L2_NANDSendAddr(2,Addr);
else
L2_NANDSendAddr(3,Addr);
//patch4.5@ada@Add timeout count begin
//Status = 0x01;
//while(Status!=0) L2_NANDCheckRdy(&Status);
L2_NANDCheckRdy(&error);
if (error != 0)
{
return error;
}
//patch4.5@ada@Add timeout count end
L2_ECCMode(0);
L2_ClearECC();
//patch4.5@ada@Add timeout count begin
if (Dst == 1)
{
L2_SetSRAMDMA(0x0C00);
}
error = L2_DoDMA(2,Dst,PageSize,0,0);
if (error != 0)
{
return error;
}
//patch4.5@ada@Add timeout count end
L2_ReadECC(ECCCnt,ECCData);
for(tmp0=0; tmp0<ECCCnt; tmp0++)
{
L2_NANDReadPort(&ByteData);
if(ECCData[tmp0] != ByteData) error = 1;
}
L2_NANDCompleteOperation();
if(Dst == 0) dramaddr += (ULONG)(PageSize>>1);
Addr++;
}
//PRINT_L1(" L1_DMARdNAND: Exit L1_DMARdNAND(error = %x)\n",(USHORT)error);
return error;
}
#if (CFAIDE)
/*++
Copyright (c) 2001 Sunplus Technology Co., Ltd.
Module Name:
L1_CF.c
Abstract:
Module related to L1 CF card functions
Environment:
Keil C51 Compiler
Revision History:
11/12/2001 WZH created
--*/
//=============================================================================
//Program
//=============================================================================
//-----------------------------------------------------------------------------
//L1_DMAWrCFIDE
//-----------------------------------------------------------------------------
/*
routine description:
DMA write data to CF card in IDE mode
arguments:
Src: the source of DMA
0: DRAM
1: CPU 4K SRAM (0x1000 ~ 0x1FFF)
2: forbidden (flash itself)
3: Audio
4: USB
5: DMA data port (0x2300)
CylHigh: CF card register: cylinder high
CylLow: CF card register: cylinder low
SecNum: CF card register: sector number
SecSize: the number of byte in a sector
SecCnt: the number of sector
return value:
TRUE - success
FALSE - error
*/
//ada@0312
UCHAR L1_DMAWrCFIDE(UCHAR Src, UCHAR HS, UCHAR CylHigh, UCHAR CylLow, UCHAR SecNum, ULONG SecCnt, USHORT SecSize) USING_0
{
UCHAR Ready;
USHORT WordData;
UCHAR Haddr;
UCHAR Scnt;
USHORT tmp;
ULONG dramaddr;
ULONG i;
//patch4.5@ada@Add timeout count begin
USHORT timeout_count = 0xffff;
UCHAR error;
//patch4.5@ada@Add timeout count end
if (Src == 0)
{
L2_ReadDRAMDMAAdr(&dramaddr);
}
// check interface ready
Ready = 0x00;
while ((Ready & 0x01) != 0x00)
{
//patch4.5@ada@Add timeout count begin
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
//patch4.5@ada@Add timeout count end
L2_CFCheckRdy(&Ready);
}
Haddr = 0xE0 | (HS & 0x0F);
for (i = SecCnt; i > 256 ; i = (i - 256))
{
//check CF status register not busy and ready
//patch4.5@ada@Add timeout count begin
timeout_count = 0xffff;
WordData = 0x0000;
while ((WordData & 0x00c0) != 0x0040)
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
L2_CFSetWordCsARd(0x17,&WordData);
}
//patch4.5@ada@Add timeout count end
// Write command
L2_CFSetWordCsAWr(0x12,0x0000); // Sec Cnt
L2_CFSetWordCsAWr(0x13,(USHORT)SecNum); // Sec Nu.
L2_CFSetWordCsAWr(0x14,(USHORT)CylLow); // CylLow
L2_CFSetWordCsAWr(0x15,(USHORT)CylHigh); // CylHigh
L2_CFSetWordCsAWr(0x16,(USHORT)Haddr); // logical block address is selected
// Write Sector command
L2_CFSetWordCsAWr(0x17,0x0031);
// DMA
for (tmp = 0; tmp < 256; tmp++)
{
//patch4.5@ada@Add timeout count begin
timeout_count = 0xffff;
WordData = 0x0000;
while (WordData != 0x0058)
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
L2_CFSetWordCsARd(0x17,&WordData); // check if busy
}
//patch4.5@ada@Add timeout count end
if (Src == 0)
{
L2_SetDRAMDMA(dramaddr);
}
L2_CFSetCsA(0x10);
//richie@mi 0411 mark
//L2_DoDMA(Src,2,SecSize,0,0);
//richie@mi 0411 begin
if (Src != K_DMA_USB)
{
// sync mode
//patch4.5@ada@Add timeout count begin
if (Src == 1)
{
L2_SetSRAMDMA(0x0C00);
}
error = L2_DoDMA(Src,2,SecSize,0,0);
if (error != 0)
{
return FALSE;
}
//patch4.5@ada@Add timeout count end
}
else
{
UCHAR bi;
//patch4.5@ada@Add timeout count begin
// async mode
error = L2_DoDMA(Src,2,SecSize,1,0);
if (error != 0)
{
return FALSE;
}
//patch4.5@ada@Add timeout count end
for (bi=0;bi<8;bi++)
{
//patch4.5@richie@msdc plug out exception
while ((XBYTE[K_USB_CLASS_OUT_BUF_SIZE] > 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait for 0 in bulk buffer
XBYTE[0x25a1] = K_USB_CLASS_OUT_OPEN;//0x02;//open bulk out
//patch4.5@richie@msdc plug out exception
while (((XBYTE[0x25c2] & K_USB_CLASS_OUT_ACK_MASK) == 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait pc ack
XBYTE[0x25c2] = XBYTE[0x25c2] & K_USB_CLASS_OUT_ACK_RESET;//reset 0x25c2
}
//patch4.5@richie@msdc plug out exception
while ((XBYTE[K_USB_CLASS_OUT_BUF_SIZE] > 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait for 0 in bulk buffer
}
//richie@mi 0411 end
//patch4.5@ada@Add timeout count begin
timeout_count = 0xffff;
WordData = 0x0000;
while ((WordData & 0x00c0) != 0x0040) //check CF status register not busy and ready
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
L2_CFSetWordCsARd(0x17,&WordData);
}
//patch4.5@ada@Add timeout count end
if (Src == 0)
{
dramaddr += (ULONG)(SecSize >> 1);
}
}
if ((CylLow == 255) && (CylHigh == 255))
{
Haddr++;
CylHigh = 0x00;
CylLow = 0x00;
}
else
{
if (CylLow == 255)
{
CylHigh++;
CylLow = 0x00;
}
else
{
CylLow++;
}
}
}
if (i != 0)
{
//check CF status register not busy and ready
//patch4.5@ada@Add timeout count begin
timeout_count = 0xffff;
WordData = 0x0000;
while ((WordData & 0x00c0) != 0x0040)
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
L2_CFSetWordCsARd(0x17,&WordData);
}
//patch4.5@ada@Add timeout count end
if (i == 256)
{
Scnt = 0;
}
else
{
Scnt = (UCHAR)i;
}
// Write command
L2_CFSetWordCsAWr(0x12,(USHORT)Scnt); // Sec Cnt
L2_CFSetWordCsAWr(0x13,(USHORT)SecNum); // Sec Nu.
L2_CFSetWordCsAWr(0x14,(USHORT)CylLow); // CylLow
L2_CFSetWordCsAWr(0x15,(USHORT)CylHigh); // CylHigh
L2_CFSetWordCsAWr(0x16,(USHORT)Haddr);
// Write Sector command
L2_CFSetWordCsAWr(0x17,0x0031);
// DMA
for (tmp = 0; tmp < i ; tmp++)
{
//patch4.5@ada@Add timeout count begin
timeout_count = 0xffff;
WordData = 0x0000;
while (WordData != 0x0058)
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
L2_CFSetWordCsARd(0x17,&WordData); // check if busy
}
//patch4.5@ada@Add timeout count end
if (Src == 0)
{
L2_SetDRAMDMA(dramaddr);
}
L2_CFSetCsA(0x10);
//richie@mi 0411 mark
//L2_DoDMA(Src,2,SecSize,0,0);
//richie@mi 0411 begin
if (Src != K_DMA_USB)
{
// sync mode
//patch4.5@ada@Add timeout count begin
if (Src == 1)
{
L2_SetSRAMDMA(0x0C00);
}
error = L2_DoDMA(Src,2,SecSize,0,0);
if (error != 0)
{
return FALSE;
}
//patch4.5@ada@Add timeout count end
}
else
{
UCHAR bi;
// async mode
//patch4.5@ada@Add timeout count begin
error = L2_DoDMA(Src,2,SecSize,1,0);
if (error != 0)
{
return FALSE;
}
//patch4.5@ada@Add timeout count end
for (bi=0;bi<8;bi++)
{
//patch4.5@richie@msdc plug out exception
while ((XBYTE[K_USB_CLASS_OUT_BUF_SIZE] > 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait for 0 in bulk buffer
XBYTE[0x25a1] = K_USB_CLASS_OUT_OPEN;//0x02;//open bulk out
//patch4.5@richie@msdc plug out exception
while (((XBYTE[0x25c2] & K_USB_CLASS_OUT_ACK_MASK) == 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait pc ack
XBYTE[0x25c2] = XBYTE[0x25c2] & K_USB_CLASS_OUT_ACK_RESET;//reset 0x25c2
}
//patch4.5@richie@msdc plug out exception
while ((XBYTE[K_USB_CLASS_OUT_BUF_SIZE] > 0) && (G_UI_USBConnect == K_UI_USB_CONNECT)) ; //wait for 0 in bulk buffer
}
//richie@mi 0411 end
//check CF status register not busy and ready
//patch4.5@ada@Add timeout count begin
timeout_count = 0xffff;
WordData = 0x0000;
while ((WordData & 0x00c0) != 0x0040)
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return FALSE;
}
L2_CFSetWordCsARd(0x17,&WordData);
}
//patch4.5@ada@Add timeout count end
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