l2_dram.c

台湾凌阳方案300万数码相机源代码

        //body
        XBYTE[0x270e]=ImgType;

        //return
        return(status);
}

//-----------------------------------------------------------------------------
//L2_SetDisplayMode
//-----------------------------------------------------------------------------
/*
routine description:
                Control the frame rate conversion.
arguments:
                Frcen      0 - Disable the auto frame rate conversion
                           1 - Enable the auto frame rate conversion. The Option arguments
                               is unaffective if the Frcen is set to 1.
                Option[0]  0 - Sensor input is faster than LCD
                           1 - Sensor input is slower than LCD
                      [4]  0 - LCD display is based on the frame buffer A
                           1 - LCD display is based on the frame buffer B
                      [5]  0 - Sensor data is writen to the frame buffer A
                           1 - Sensor dara is writen to the frame buffer B
                      [6]  0 - JPEG compress from and decompress to the frame buffer A
                           1 - JPEG compress from and decompress to the frame buffer B
return value:
                0x00    - success
                others  - error
*/

UCHAR L2_SetDisplayMode(UCHAR Frcen, UCHAR Option) USING_0
{
        UCHAR status = L2K_SUCCESS;
        UCHAR frcmode,lcdidx,ccdidx,jpgidx;

        //body
        frcmode=(Option)&0x01;
        lcdidx =(Option>>4)&0x01;
        ccdidx =(Option>>5)&0x01;
        jpgidx =(Option>>6)&0x01;

        if(Frcen==0x01) //enable frame rate conversion
        {
         XBYTE[0x2746]=1;
         XBYTE[0x2747]=frcmode;
        }
        else            //disable frame rate conversion
        {
         XBYTE[0x2746]=0;
         XBYTE[0x2748]=lcdidx;
         XBYTE[0x2749]=ccdidx;
         XBYTE[0x274a]=jpgidx;
        }
        //return
        return(status);
}


//-----------------------------------------------------------------------------
//L2_ClrVLCrdy
//-----------------------------------------------------------------------------
/*
routine description:
                Clear the vlcardy or vlcbrdy flag
arguments:
                Target 0 - clear the vlcardy
                       1 - clear the vlcbrdy
return value:
                0x00     - success
                others   - error
*/
UCHAR L2_ClrVLCRdy(UCHAR Target) USING_0
{
        UCHAR status = L2K_SUCCESS;

        //body
        if(Target==0)
          XBYTE[0x2715]=0x00;   //clear vlcardy
        else
          XBYTE[0x2716]=0x00;   //clear vlcbrdy

        //return
        return(status);
}

//-----------------------------------------------------------------------------
//L2_SelDRAMRefreshSrc
//-----------------------------------------------------------------------------
/*
routine description:
                Select the SDRAM auto refresh source
arguments:
                Source 0 - auto refresh is based on the TG h-sync signal
                       1 - auto refresh is based on the LCD h-sync signal
                       2 - auto refresh is based on the counter built in
                           the SDRAM controller itself
return value:
                0x00     - success
                others   - error
*/
UCHAR L2_SelDRAMRefreshSrc(UCHAR Source) USING_0
{
        UCHAR status = L2K_SUCCESS;

        //body
        if(Source==0)      XBYTE[0x2717]=0x00;    // auto-refresh by TG h-sync
        else if(Source==1) XBYTE[0x2717]=0x01;    // auto-refresh by LCD h-sync
        else               XBYTE[0x2717]=0x02;    // auto-refresh by built-in counter

        //return
        return(status);
}

//-----------------------------------------------------------------------------
//L2_EnterExitSelfRefresh
//-----------------------------------------------------------------------------
/*
routine description:
                Fource the SDRAM enter or exit the self-refresh mode
arguments:
                Mode 0 - Enter the self-refresh mode
                     1 - Exit the self-refresh mode
return value:
                0x00   - success
                others - error
*/
UCHAR L2_EnterExitSelfRefresh(UCHAR Mode) USING_0
{
        UCHAR status = L2K_SUCCESS;

        //body
        if(Mode==0) XBYTE[0x2708]=1;    // enter self-refresh mode
        else        XBYTE[0x2708]=0;    // exit self-refresh mode

        //return
        return(status);
}


//-----------------------------------------------------------------------------
//L2_SetRFBSize
//-----------------------------------------------------------------------------
/*
routine description:
                Set the raw frame buffer width and height
arguments:
                FBHSize - The raw frame buffer width
                FBVSize - The raw frame buffer height
return value:
                0x00    - success
                others  - error
*/
UCHAR L2_SetRFBSize(USHORT FBHSize, USHORT FBVSize) USING_0
{
        UCHAR status = L2K_SUCCESS;

        //body
        XBYTE[0x276b]=(UCHAR)FBHSize&0xff;
        XBYTE[0x276c]=(UCHAR)(FBHSize>>8)&0x0f;  //limit the width to 4095
        XBYTE[0x276d]=(UCHAR)FBVSize&0xff;
        XBYTE[0x276e]=(UCHAR)(FBVSize>>8)&0x0f;  //limit the height to 4095

        //return
        return(status);
}

#if 0
//-----------------------------------------------------------------------------
//L2_DRAMWriteWord
//-----------------------------------------------------------------------------
/*
routine description:
                Write a word to the SDRAM
arguments:
                Addr         - The address
                LowByteData  - The low byte data to be written to the SDRAM
                HighByteData - The high byte data to be written to the SDRAM
return value:
                0x00         - success
                others       - error
*/
UCHAR L2_DRAMWriteWord(ULONG Addr, UCHAR LowByteData, UCHAR HighByteData) USING_0
{
        UCHAR status = L2K_SUCCESS;
        UCHAR cmp = 0;
        //body

        L2_SetDRAMDMA(Addr);           //set DRAM starting address
        L2_DoDMA(5, 0, 2, 1, 0);       //trigger DMA action
        L2_WriteDMAPort(LowByteData);
        L2_WriteDMAPort(HighByteData);
        while(cmp==0) L2_CheckDMACmp(&cmp);

        //return
        return(status);
}

//-----------------------------------------------------------------------------
//L2_DRAMReadWord
//-----------------------------------------------------------------------------
/*
routine description:
                Read a word from the SDRAM
arguments:
                Addr         -
                LowByteData  -
                HighByteData -
return value:
                0x00         - success
                others       - error
*/
UCHAR L2_DRAMReadWord(ULONG Addr, UCHAR *LowByteData, UCHAR *HighByteData) USING_0
{
        UCHAR status = L2K_SUCCESS;
        UCHAR size = 0;
        UCHAR cmp = 0;
        //body

        L2_SetDRAMDMA(Addr);           //set DRAM starting address
        L2_DoDMA(0, 5, 2, 1, 0);       //trigger DMA action
        while(size!=2) L2_GetDMABufSize(&size);
        L2_ReadDMAPort(LowByteData);
        L2_ReadDMAPort(HighByteData);
        while(cmp==0) L2_CheckDMACmp(&cmp);

        //return
        return(status);
}
#endif

//-----------------------------------------------------------------------------
//L2_SetCapint
//-----------------------------------------------------------------------------
/*
routine description:
                Set the capture interval
arguments:
                Interval     - Image capture interval
return value:
                0x00         - success
                others       - error
*/
UCHAR L2_SetCapint(UCHAR Interval) USING_0
{
        UCHAR status = L2K_SUCCESS;

        //body
        XBYTE[0x2739]=Interval;

        //return
        return(status);
}

//-----------------------------------------------------------------------------
//L2_CheckDRAMStatus
//-----------------------------------------------------------------------------
/*
routine description: return the DRAMCTRL status
return value : dramctrl status
*/
UCHAR L2_CheckDRAMStatus(void) USING_0
{
 return(XBYTE[0X27B0]);
}

#ifdef TestModeEn
//-----------------------------------------------------------------------------
//L2_TestSDRAM
//-----------------------------------------------------------------------------
/*
routine description:
  SDRAM module test.
arguments:
  TestLevel: the level of test

return value:
  0x00   - success
  others - error

*/
UCHAR L2_TestSDRAM(UCHAR TestLevel) USING_0
{
        UCHAR status = L2K_SUCCESS;
        USHORT i,j;
        ULONG A[3];

        //avoid warning
        UCHAR  Temp0 = TestLevel;

         #ifdef M64                     //64M SDRAM
            A[0]=1048570;
            A[1]=2097150;
            A[2]=3145720;
         #endif
         #ifdef M128                    //128M SDRAM
            A[0]=2097150;
            A[1]=4194300;
            A[2]=6291450;
         #endif
         #ifdef M256                    //256M SDRAM
            A[0]=4194300;
            A[1]=8388600;
            A[2]=12582900;
         #endif

        for(i=0;i<3;i++)
        {
          //PRINT_L2("          L2_TestSDRAM: A[%d]=%ld\n", i, A[i]);
        }

        //body
        XBYTE[0x2c00]=0x0d;             //write 256 bytes data to the 4K SRAM
        XBYTE[0x2c11]=0x00;
        XBYTE[0x2c00]=0x0f;
        for(i=0x00;i<0x100;i++)
          XBYTE[0x1000+i]=i;

        for(i=0;i<3;i++)
        {
         L2_SetSRAMDMA(0x0000);         //set SRAM starting address(offset)
         L2_SetDRAMDMA(A[i]);           //set DRAM starting address
         L2_DoDMA(1, 0, 256, 0, 0);     //trigger DMA action
        }

        for(i=0;i<3;i++)
        {
          XBYTE[0x2c00]=0x0d;           //write 256 bytes 0 to clear the 4K SRAM
          XBYTE[0x2c11]=0x00;
          XBYTE[0x2c00]=0x0f;
          for(j=0x00;j<0x100;j++)
            XBYTE[0x1000+j]=0;

          L2_SetSRAMDMA(0x0000);        //set SRAM starting address
          L2_SetDRAMDMA(A[i]);          //set DRAM starting address
          L2_DoDMA(0, 1, 256, 0, 0);    //trigger DMA action

          XBYTE[0x2c00]=0x0d;           //read 256 bytes from the 4K SRAM
          XBYTE[0x2c11]=0x00;
          XBYTE[0x2c00]=0x0f;

          j=0;
          while((XBYTE[0x1000+j]==j)&&(j<0x100))
            j=j+1;

          if(j==0x100)
          {
                //PRINT_L2("            L2_TestSDRAM: SDRAM check successfully...\n");
          }
          else
          {
           //PRINT_L2("            L2_TestSDRAM: SDRAM check fail...\n");
           //PRINT_L2("            L2_TestSDRAM: fail address=%ld\n", (A[i]+(ULONG)j));
          }
         }

        //return
        return(status);
}

#endif