l2_dmac.c

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/*++

Copyright (c) 2001 Sunplus Technology Co., Ltd.

Module Name:

        L2_dmac.c

Abstract:

        Module related to L2 DMAC functions

Environment:

        Keil C51 Compiler

Revision History:

        11/12/2001      WZH    created                 

--*/
//=============================================================================
//Header file
//=============================================================================
#include "general.h"

//=============================================================================
//Symbol
//=============================================================================
//-----------------------------------------------------------------------------
//Constant
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
//Variable
//-----------------------------------------------------------------------------

//=============================================================================
//Program       
//=============================================================================

//-----------------------------------------------------------------------------
//L2_DoDMA
//-----------------------------------------------------------------------------
/* 
routine description:
        DMA data transfer, the source and the desitination cannot be the same
arguments:
        Src: the source of DMA
                0: DRAM
                1: CPU 4K SRAM (0x1000 ~ 0x1FFF)
                2: Storage Media
                3: Audio
                4: USB
                5: DMA data port (0x2300)
        Dst: the destination of DMA
                0: DRAM
                1: CPU 4K SRAM (0x1000 ~ 0x1FFF)
                2: Storage Media
                3: Audio
                4: USB
                5: DMA data port (0x2300)
        nByte: the number of byte in the DMA data transfer (tha maximum size is 1024)
        Mode: 
                0: the function return after the DMA is completed
                1: the function return immediately after the DMA is trigger (SRAM client is restricted)
        FlashPageDMA
                0: normal operation
                1: if flash is one of the DMA source/destination, flash accessing is always in the unit of page
                        the insufficent data is stuffing by 0's
return value:	   
        0x00   - success
        others - error
*/
UCHAR L2_DoDMA(UCHAR Src,UCHAR Dst, USHORT nByte, UCHAR Mode, UCHAR FlashPageDMA) USING_0
{
     data UCHAR sramflag; 	// WWWW
	data UCHAR dmamode;	// WWWW

	//patch4.5@ada@Add timeout count begin
	data USHORT timeout_count = 0xffff;
	//patch4.5@ada@Add timeout count end
        //PRINT_L2("        L2_DoDMA: Enter L2_DoDMA(Src=%x,Dst=%x,nByte=%x,Mode=%x,FlashPageDMA=%x)\n",(USHORT)Src,(USHORT)Dst,nByte,(USHORT)Mode,(USHORT)FlashPageDMA);

	nByte = nByte - 1;
     dmamode = Mode;

	XBYTE[0x2301] = (Dst<<4)|Src;

     XBYTE[0x2304] = 0x09;                                // reset DMA machine
	XBYTE[0x2304] = 0x08;
     XBYTE[0x23C0] = 0x00;

     if (FlashPageDMA)
	{   
		XBYTE[0x2304] |= 0x02;            // padding 0's to flash
	}
	else
	{
          XBYTE[0x2304] &= 0xfd;
	}

	if ((nByte>>10)!=0)
	{
		return L2K_ERROR_GENERAL;                      // DMA size
	}

     XBYTE[0x2302] = (UCHAR)nByte&0xff;
	XBYTE[0x2303] = (UCHAR)(nByte>>8)&0x03;

	sramflag = 0;

     if(Src==0x01 || Dst==0x01)
     {
          XBYTE[0x2C00] &= 0x1d;
          XBYTE[0x2C11]  = 0x02;
          XBYTE[0x2C00] |= 0x02;
          sramflag = 1;
     }

     XBYTE[0x23B0] = 0x01;                                // trigger DMA

	if (dmamode)
	{
		return L2K_SUCCESS;
	}
	else
	{
		//patch4.5@ada@Add timeout count begin
		while(XBYTE[0x23C0]==0)                       // wait for DMA complete
		{
			if (timeout_count > 0)
			{
				timeout_count--;
			}
			else
			{
			    if (sramflag == 1)
				{
					L2_Set4KSRAMMode(0x00);
				}

				return L2K_ERROR_GENERAL;
			}
		}
		//patch4.5@ada@Add timeout count end
	}

	XBYTE[0x23C0] = 0x00;

     if (sramflag == 1)
     {
          XBYTE[0x2C00] &= 0x1d;
          XBYTE[0x2C11]  = 0x00;
          XBYTE[0x2C00] |= 0x02;
     }

     //PRINT_L2("        L2_DoDMA: Exit L2_DoDMA\n");
     return L2K_SUCCESS;
}

//-----------------------------------------------------------------------------
//L2_ResetDMA
//-----------------------------------------------------------------------------
/* 
routine description:
        Reset DMA controller 
*/
void L2_ResetDMA(void) USING_0
{
        //PRINT_L2("        L2_ResetDMA: Enter L2_ResetDMA\n");

     XBYTE[0x2310] = 0x10;
     XBYTE[0x2304] = 0x09;    
	XBYTE[0x2304] = 0x08;

        //PRINT_L2("        L2_ResetDMA: Exit L2_ResetDMA\n");
}

//-----------------------------------------------------------------------------
//L2_CheckDMACmp
//-----------------------------------------------------------------------------
/* 
routine description:
        Check whether DMA is complete.
        If DMA is completed, clear the flag and report
arguments:
        Cmp:
                0: DMA is not completed
                1: DMA is completed
*/
void L2_CheckDMACmp(UCHAR* Cmp) USING_0
{
        //PRINT_L2("        L2_CheckDMACmp: Enter L2_CheckDMACmp\n");

        *Cmp = XBYTE[0x23C0];
        if(*Cmp) XBYTE[0x23C0] = 0x00; 

        //PRINT_L2("        L2_CheckDMACmp: Exit L2_CheckDMACmp\n");
}

//-----------------------------------------------------------------------------
//L2_GetDMABufSize
//-----------------------------------------------------------------------------
/* 
routine description:
        get the size of DMA remainding buffer
arguments:
        BufSize: the remainding buffer size (maximum is 4 bytes)
*/
void L2_GetDMABufSize(UCHAR* BufSize) USING_0
{
        //PRINT_L2("        L2_GetDMABufSize: Enter L2_GetDMABufSize\n");

        *BufSize = XBYTE[0x23A0]&0x07;

        //PRINT_L2("        L2_GetDMABufSize: Exit L2_GetDMABufSize\n");
}

//-----------------------------------------------------------------------------
//L2_WriteDMAPort
//-----------------------------------------------------------------------------
/* 
routine description:
        write data to DMA port
arguments:
        PortData: write data    
*/
void L2_WriteDMAPort(UCHAR PortData) USING_0
{
        //PRINT_L2("        L2_WriteDMAPort: Enter L2_WriteDMAPort(PortData=%x)\n",(USHORT)PortData);

        XBYTE[0x2300] = PortData;

        //PRINT_L2("        L2_WriteDMAPort: Exit L2_WriteDMAPort\n");
}

//-----------------------------------------------------------------------------
//L2_ReadDMAPort
//-----------------------------------------------------------------------------
/* 
routine description:
        read data from DMA port
arguments:
        PortData: read data    
*/
void L2_ReadDMAPort(UCHAR* PortData) USING_0
{
        //PRINT_L2("        L2_ReadDMAPort: Enter L2_ReadDMAPort\n");

        *PortData = XBYTE[0x2300];

        //PRINT_L2("        L2_ReadDMAPort: Exit L2_ReadDMAPort\n");
}

//-----------------------------------------------------------------------------
//L2_SetDRAMDMA
//-----------------------------------------------------------------------------
/* 
routine description:
        DRAM DMA setting
arguments:
        DRAMAddr: DRAM starting address
return value:
        0x00   - success
        others - error
*/
UCHAR L2_SetDRAMDMA(ULONG DRAMAddr) USING_0
{
        //PRINT_L2("        L2_SetDRAMDMA: Enter L2_SetDRAMDMA(DRAMAddr=%lx)\n",DRAMAddr);

        XBYTE[0x2750] = (UCHAR)DRAMAddr&0xff;
	XBYTE[0x2751] = (UCHAR)(DRAMAddr>>8)&0xff;
        XBYTE[0x2752] = (UCHAR)(DRAMAddr>>16)&0xff;