asicreg.h

台湾凌阳方案300万数码相机源代码

#ifndef _asicreg_
#define _asicreg_

#include "chipopt.h"

// wyeo@0527, patch 4.2, whole file

// 8051 Macro
#if (K_HAVE_L2)
#define M_ENABLE_8051_INT
#define M_DISABLE_8051_INT
#else	
#define M_ENABLE_8051_INT		ET0 = 1
#define M_DISABLE_8051_INT		ET0 = 0
#endif

//-------------------------------------
//500
//-------------------------------------
#if ( K_CHIP_SET == K_CHIP_500 )
// register index and name mapping
#define K_REG_DRAM_Control		(0x870a)
#define K_REG_DRAM_Status		(0x870b)
#define K_REG_DRAM_LsbByte		(0x8700)
#define K_REG_DRAM_MsbByte		(0x8701)

#define K_REG_DRAM_StRowLow		(0x8702)
#define K_REG_DRAM_StRowHigh		(0x8703)
#define K_REG_DRAM_StColLow		(0x8704)
#define K_REG_DRAM_StColHigh		(0x8705)

#define K_REG_DRAM_EndRowLow		(0x8706)
#define K_REG_DRAM_EndRowHigh		(0x8707)
#define K_REG_DRAM_EndColLow		(0x8708)
#define K_REG_DRAM_EndColHigh		(0x8709)

#define K_REG_QTABLE			(0x8800)

#define M_REG_DRAM_StColHigh		XBYTE[K_REG_DRAM_StColHigh]

#define M_REG_DRAM_EndRowLow		XBYTE[K_REG_DRAM_EndRowLow]
#define M_REG_DRAM_EndRowHigh		XBYTE[K_REG_DRAM_EndRowHigh]
#define M_REG_DRAM_EndColLow		XBYTE[K_REG_DRAM_EndColLow]
#define M_REG_DRAM_EndColHigh		XBYTE[K_REG_DRAM_EndColHigh]

//-------------------------------------
//503
//-------------------------------------
#elif ( K_CHIP_SET == K_CHIP_503 )

// register index and name mapping
#define K_REG_DRAM_Control		(0x27a0)
#define K_REG_DRAM_Status		(0x27b0)
#define K_REG_DRAM_LsbByte		(0x2700)
#define K_REG_DRAM_MsbByte		(0x2701)

#define K_REG_DRAM_StRowLow		(0x2702)
#define K_REG_DRAM_StRowHigh		(0x2703)
#define K_REG_DRAM_StColLow		(0x2704)

#define K_REG_QTABLE			(0x2800)

//-------------------------------------
//504
//-------------------------------------
#elif ( K_CHIP_SET == K_CHIP_504 )
// register index and name mapping
#define K_REG_DRAM_Control		(0x27a0)
#define K_REG_DRAM_Status		(0x27b0)
#define K_REG_DRAM_LsbByte		(0x2700)
#define K_REG_DRAM_MsbByte		(0x2701)

#define K_REG_DRAM_StRowLow		(0x2702)
#define K_REG_DRAM_StRowHigh		(0x2703)
#define K_REG_DRAM_StColLow		(0x2704)

#define K_REG_QTABLE			(0x2800)

//-------------------------------------
//533
//-------------------------------------
#elif ( K_CHIP_SET == K_CHIP_533 )

// register index and name mapping
#define K_REG_DRAM_Control		(0x27a0)
#define K_REG_DRAM_Status		(0x27b0)
#define K_REG_DRAM_LsbByte		(0x2700)
#define K_REG_DRAM_MsbByte		(0x2701)

#define K_REG_DRAM_StRowLow		(0x2720)
#define K_REG_DRAM_StRowHigh		(0x2721)
#define K_REG_DRAM_StColLow		(0x2722)

#define K_REG_QTABLE			(0x2800)

#endif

#define K_REG_DRAM_Control_Prefetch	(0x01)

// register name
#define M_REG_DRAM_Status		XBYTE[K_REG_DRAM_Status]
#define M_REG_DRAM_Control		XBYTE[K_REG_DRAM_Control]
#define M_REG_DRAM_LsbByte		XBYTE[K_REG_DRAM_LsbByte]
#define M_REG_DRAM_MsbByte		XBYTE[K_REG_DRAM_MsbByte]

#define M_REG_DRAM_StRowLow		XBYTE[K_REG_DRAM_StRowLow]
#define M_REG_DRAM_StRowHigh		XBYTE[K_REG_DRAM_StRowHigh]
#define M_REG_DRAM_StColLow		XBYTE[K_REG_DRAM_StColLow]

#define M_REG_QTABLE			XBYTE[K_REG_QTABLE]

// Macro
#define M_DRAM_WaitReady		while ( ( M_REG_DRAM_Status & 0x01 ) != 0x00)
#define M_DRAM_PrefetchOn		M_REG_DRAM_Control = K_REG_DRAM_Control_Prefetch

//wyeo@0527, patch 4.2
#if (K_CHIP_SET == K_CHIP_500)
#define M_DRAM_CardSetStartAddress(a,b)		M_REG_DRAM_StRowLow = (a);        \
                                        	M_REG_DRAM_StRowHigh = (a)>>8;    \
                                        	M_REG_DRAM_StColLow = (a)>>16;    \
                                        	M_REG_DRAM_StColHigh = (a)>>24;   \
                                        	G_DOS_SDRAM_NextIntRetAddr = a;\
                                        	if ((b)) {M_DRAM_PrefetchOn; G_File_SDRAM_Read = 1} else G_File_SDRAM_Read = 0; 
                                             		
#define M_DRAM_SetStartAddress(a,b)     M_REG_DRAM_StRowLow = (a);        \
                                        M_REG_DRAM_StRowHigh = (a)>>8;    \
                                        M_REG_DRAM_StColLow = (a)>>16;    \
                                        M_REG_DRAM_StColHigh = (a)>>24;   \
                                        if ((b)) M_DRAM_PrefetchOn; 
                                             
#else
#define M_DRAM_CardSetStartAddress(a,b)		M_REG_DRAM_StRowLow = (a);        \
                                        	M_REG_DRAM_StRowHigh = (a)>>8;    \
                                        	M_REG_DRAM_StColLow = (a)>>16;    \
                                        	G_DOS_SDRAM_NextIntRetAddr = a;\
                                        	if ((b)) {M_DRAM_PrefetchOn; G_File_SDRAM_Read = 1;} else G_File_SDRAM_Read = 0;


#define M_DRAM_SetStartAddress(a,b)     M_REG_DRAM_StRowLow = (a);        \
                                        M_REG_DRAM_StRowHigh = (a)>>8;    \
                                        M_REG_DRAM_StColLow = (a)>>16;    \
                                        if ((b)) M_DRAM_PrefetchOn;
                                              
#endif
                                              
#define M_DRAM_WriteWord(a, b)		M_REG_DRAM_LsbByte = a;	\
					M_REG_DRAM_MsbByte = b; \
					M_DRAM_WaitReady;
					
#define M_DRAM_ReadWord(a, b)		M_DRAM_WaitReady;		\
					a = M_REG_DRAM_LsbByte;		\
					b = M_REG_DRAM_MsbByte;

#if (K_HAVE_L2)
#define M_AUDIO_DISABLE_8051_INT
#define M_AUDIO_ENABLE_8051_INT	
#else
#if (AUDIO_OPTION == 1)
#define M_AUDIO_DISABLE_8051_INT	if (G_File_AudioEnable)		\
        					M_DISABLE_8051_INT;
#else
#define M_AUDIO_DISABLE_8051_INT
#endif

#if (AUDIO_OPTION == 1)
#define M_AUDIO_ENABLE_8051_INT		if (G_File_AudioEnable)		\
        					M_ENABLE_8051_INT;
#else
#define M_AUDIO_ENABLE_8051_INT
#endif
#endif

// HIS101c-0002 end

#endif