📄 l2_lcdtv.c
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XBYTE[0x2D09] = 0x00; // vldx0
XBYTE[0x2D0A] = 0x10; // vldy0
XBYTE[0x2D0B] = 0x00; // vldy0
XBYTE[0x2D0C] = 0x0F; // vldx1
XBYTE[0x2D0D] = 0x03; // vldx1
XBYTE[0x2D0E] = 0xEF; // vldy1
XBYTE[0x2D0F] = 0x01; // vldy1
XBYTE[0x2D1B] = 0x00; // imgvofst
XBYTE[0x2D1C] = 0x00; // imgvofst
XBYTE[0x2D1D] = 0x00; // imghofst
XBYTE[0x2D1E] = 0x00; // imghofst
XBYTE[0x2D33] = 0x20; // osdvofst
XBYTE[0x2D34] = 0x20; // osdhofst
XBYTE[0x2D21] = 0x40; // osdsubsamp
XBYTE[0x2D33] = 0x00; // osdvofst
XBYTE[0x2D34] = 0x20; // osdhofst
//patch4.3@yichang@0613 for TV sharpness
//XBYTE[0x2DE2] = 0x00; // field mode
XBYTE[0x2DE2] = 0x02; // field mode
status = 0;
}
//#endif
//#ifdef AU015AN02
if(index==13)// AU015AN02 output
{
XBYTE[0x201C] = 0x02; // using 27MHz for AU digital I/F TFT-LCD
XBYTE[0x20E6] = 0x80; // phase adjustment
XBYTE[0x2D00] = 0x09; // tvdspmode
XBYTE[0x2D02] = 0x05; // vline
XBYTE[0x2D03] = 0x01; // vline
XBYTE[0x2D04] = 0x59; // hpixel
XBYTE[0x2D05] = 0x03; // hpixel
XBYTE[0x2D06] = 0x15; // vsyncw
XBYTE[0x2D07] = 0x11; // hsyncw
//patch5.2.1@ada@Fix the bug of AVI recording with blue line on the left side begin
XBYTE[0x2D08] = 0x82; // vldx0
//XBYTE[0x2D08] = 0x86; // vldx0
//patch5.2.1@ada@Fix the bug of AVI recording with blue line on the left side end
XBYTE[0x2D09] = 0x00; // vldx0
XBYTE[0x2D0A] = 0x03; // vldy0
XBYTE[0x2D0B] = 0x00; // vldy0
XBYTE[0x2D0C] = 0xE0; // vldx1
XBYTE[0x2D0D] = 0x02; // vldx1
XBYTE[0x2D0E] = 0xDE; // vldy1
XBYTE[0x2D0F] = 0x00; // vldy1
XBYTE[0x2D1B] = 0x00; // imgvofst
XBYTE[0x2D1C] = 0x00; // imgvofst
XBYTE[0x2D1D] = 0x00; // imghofst
XBYTE[0x2D1E] = 0x00; // imghofst
XBYTE[0x2D20] = 0x20; // imgsubsamp
XBYTE[0x2D21] = 0x20; // osdsubsamp
XBYTE[0x2D26] = 0x08; // osdsubsamp
XBYTE[0x2D33] = 0x00; // osdvofst
XBYTE[0x2D34] = 0x3A; // osdhofst
//patch4.3@yichang@0613 for TV sharpness
//XBYTE[0x2DE2] = 0x00; // field mode
XBYTE[0x2DE2] = 0x02; // field mode
status = 0;
}
//#endif
//#ifdef STNLCD160
if(index==14)// GiantPlus output
{
//patch4.2@richie@0523 begin
//patch4.5@richie@hue begin
XBYTE[0x2D2B] |= 0x01; //enable gamma //cytsai@0328
//XBYTE[0x21AE] = 0x30; //saturation //cytsai@0328
//patch4.5@richie@hue end
//patch4.5@richie@saturation begin
//XBYTE[0x21AE] = 0x01; //enable saturation and hue adjustment //cytsai@0328
XBYTE[0x21AC] |= 0x01; //enable saturation and hue adjustment //cytsai@0328
//patch4.5@richie@saturation end
// patch 5.2.1_32@mattwang@fix STNLCD160 & STNLCD128 setting beg
XBYTE[0x21AE]= 0x58; // saturation // 20040423 mattwang add
XBYTE[0x201C] = 0x00; // using 27MHz for STN-LCD // 20040423 mattwang modify
XBYTE[0x2D20] = 0x40; // imgsubsamp // 20040422 mattwang add
XBYTE[0x2D00] = 0x0C; // tvdspmode
XBYTE[0x2D02] = 0xA5; // vline
XBYTE[0x2D03] = 0x00; // vline
XBYTE[0x2D04] = 0x1F; // hpixel
XBYTE[0x2D05] = 0x01; // hpixel
// XBYTE[0x201C] = 0x02; // using 24MHz for STN-LCD
// XBYTE[0x2D00] = 0x0C; // tvdspmode
// XBYTE[0x2D02] = 0x7d; // vline
// XBYTE[0x2D03] = 0x00; // vline
// XBYTE[0x2D04] = 0xCF; // hpixel
// XBYTE[0x2D05] = 0x00; // hpixel
// patch 5.2.1_32@mattwang@fix STNLCD160 & STNLCD128 setting end
//patch4.2@richie@0523 end
XBYTE[0x2D06] = 0x02; // vsyncw
XBYTE[0x2D07] = 0x08; // hsyncw
XBYTE[0x2D08] = 0x28; // vldx0
XBYTE[0x2D09] = 0x00; // vldx0
XBYTE[0x2D0A] = 0x04; // vldy0
XBYTE[0x2D0B] = 0x00; // vldy0
XBYTE[0x2D0C] = 0xC7; // vldx1
XBYTE[0x2D0D] = 0x00; // vldx1
XBYTE[0x2D0E] = 0x7b; // vldy1
XBYTE[0x2D0F] = 0x00; // vldy1
XBYTE[0x2D1B] = 0x00; // imgvofst
XBYTE[0x2D1C] = 0x00; // imgvofst
XBYTE[0x2D1D] = 0x00; // imghofst
XBYTE[0x2D1E] = 0x00; // imghofst
XBYTE[0x2D26] = 0x02; // odd , even line
XBYTE[0x2D21] = 0x40; // osdsubsamp
XBYTE[0x2D33] = 0x00; // osdvofst
XBYTE[0x2D34] = 0x20; // osdhofst
//patch4.3@yichang@0613 for TV sharpness
//XBYTE[0x2DE2] = 0x00; // field mode
XBYTE[0x2DE2] = 0x02; // field mode
status = 0;
}
//#endif
//#ifdef SVGAOUT
if(index==15)// 800X600 SVGA output
{
XBYTE[0x201C] = 0x00; // using 27MHz for TV
XBYTE[0x2D00] = 0x0F; // tvdspmode
XBYTE[0x2D02] = 0x70; // vldx0
XBYTE[0x2D03] = 0x02; // vldx0
XBYTE[0x2D04] = 0x59; // vldx0
XBYTE[0x2D05] = 0x03; // vldx0
XBYTE[0x2D06] = 0x06; // vldx0
XBYTE[0x2D07] = 0x20; // vldx0
XBYTE[0x2D08] = 0x2F; // vldx0
XBYTE[0x2D09] = 0x00; // vldx0
XBYTE[0x2D0A] = 0x03; // vldy0
XBYTE[0x2D0B] = 0x00; // vldy0
XBYTE[0x2D0C] = 0x4E; // vldx1
XBYTE[0x2D0D] = 0x03; // vldx1
XBYTE[0x2D0E] = 0x5A; // vldy1
XBYTE[0x2D0F] = 0x02; // vldy1
XBYTE[0x2D19] = 0x20; // imgvofst
XBYTE[0x2D20] = 0x40; // imgvofst
XBYTE[0x2D2A] = 0x02; // ccirtype
status = 0;
}
// #endif
//#ifdef AU015BL01 //patch5.2.1@cwh@AU015BL01;2003/08/08
if(index==16)// AU015BL01 output
{
//lirw add@0714
ThreeWire_WriteMsb16Data(0x0003);
ThreeWire_WriteMsb16Data(0x0118);
ThreeWire_WriteMsb16Data(0x0204);
ThreeWire_WriteMsb16Data(0x0340);
ThreeWire_WriteMsb16Data(0x040B);
ThreeWire_WriteMsb16Data(0x0577);
ThreeWire_WriteMsb16Data(0x0615);
ThreeWire_WriteMsb16Data(0x071e);
ThreeWire_WriteMsb16Data(0x0805);
XBYTE[0x201C] = 0x02; // using 24MHz for unipac TFT-LCD
XBYTE[0x2D00] = 0x08; // tvdspmode
XBYTE[0x2D02] = 0x07; // vline //263
XBYTE[0x2D03] = 0x01; // vline
XBYTE[0x2D04] = 0x37; // hpixel //823
XBYTE[0x2D05] = 0x03; // hpixel
XBYTE[0x2D06] = 0x01; // vsyncw
XBYTE[0x2D07] = 0x01; // hsyncw
XBYTE[0x2D08] =0x1a /*0x1f*/; // vldx0
XBYTE[0x2D09] = 0x00; // vldx0
XBYTE[0x2D0A] = 0x15; // vldy0
XBYTE[0x2D0B] = 0x00; // vldy0
XBYTE[0x2D0C] = 0x91; // vldx1
XBYTE[0x2D0D] =0x02; // vldx1
XBYTE[0x2D0E] = 0x05; // vldy1
XBYTE[0x2D0F] = 0x01; // vldy1
XBYTE[0x2D1B] = 0x00; // imgvofst
XBYTE[0x2D1C] = 0x00; // imgvofst
XBYTE[0x2D1D] = 0x00; // imghofst
XBYTE[0x2D1E] = 0x00; // imghofst
XBYTE[0x2D20] = 0x40; // imgsubsamp
XBYTE[0x2D21] = 0x27; // osdsubsamp
XBYTE[0x2D26] = 0x06; // RGB sequence
XBYTE[0x2D32] = 0x1e; // osdvzoomfactor //Hamming@2003.04.30
XBYTE[0x2D33] = 0x00; // osdvofst
XBYTE[0x2D34] = 0x1a; // osdhofst
//patch4.3@yichang@0613 for TV sharpness
//XBYTE[0x2DE2] = 0x00; // field mode
XBYTE[0x2DE2] = 0x02; // field mode
status = 0;
}
//#endif
//#ifdef TOPPOLY //patch5.2.1@cwh@Toppoly TC015TREB1;2003/08/27
if(index==17) // Toppoly TC015TREB1, CCIR601 NTSC output (8-bit)
{
//Add for Toppoly LTPS LCD begin by Hamming@2003.04.30
// patch 5.2.1_33@mattwang@rename LC15004_write to ThreeWire_WriteMsb16Data beg
ThreeWire_WriteMsb16Data(0x2052); //CCIR601
ThreeWire_WriteMsb16Data(0x0410);
ThreeWire_WriteMsb16Data(0x0504);
ThreeWire_WriteMsb16Data(0x0604);
ThreeWire_WriteMsb16Data(0x070a);
ThreeWire_WriteMsb16Data(0x1005);
ThreeWire_WriteMsb16Data(0x1101);
ThreeWire_WriteMsb16Data(0x2100);
ThreeWire_WriteMsb16Data(0x2200); //
ThreeWire_WriteMsb16Data(0x2340); //changed from 0x00 to 0x40 by Hamming
ThreeWire_WriteMsb16Data(0x2400);
ThreeWire_WriteMsb16Data(0x2530);
ThreeWire_WriteMsb16Data(0x260c);
ThreeWire_WriteMsb16Data(0x2700);
ThreeWire_WriteMsb16Data(0x7000);
ThreeWire_WriteMsb16Data(0x7150);
ThreeWire_WriteMsb16Data(0x721e);
ThreeWire_WriteMsb16Data(0x734a);
ThreeWire_WriteMsb16Data(0x7b8e);
ThreeWire_WriteMsb16Data(0x7c02);
ThreeWire_WriteMsb16Data(0x7d00);
ThreeWire_WriteMsb16Data(0x8E80);
ThreeWire_WriteMsb16Data(0x90ff);
ThreeWire_WriteMsb16Data(0x9180);
ThreeWire_WriteMsb16Data(0x9218); //20 //18
ThreeWire_WriteMsb16Data(0x9326); //32 //28
ThreeWire_WriteMsb16Data(0x9418);
ThreeWire_WriteMsb16Data(0x9500);
ThreeWire_WriteMsb16Data(0x9f23);
ThreeWire_WriteMsb16Data(0xa000);
ThreeWire_WriteMsb16Data(0xa10d);
ThreeWire_WriteMsb16Data(0xa20e);
ThreeWire_WriteMsb16Data(0xa30d);
ThreeWire_WriteMsb16Data(0xa40e);
ThreeWire_WriteMsb16Data(0xa50d);
ThreeWire_WriteMsb16Data(0xa60e);
ThreeWire_WriteMsb16Data(0xa77f);
ThreeWire_WriteMsb16Data(0xa87f);
ThreeWire_WriteMsb16Data(0xa97f);
ThreeWire_WriteMsb16Data(0xaa7f);
ThreeWire_WriteMsb16Data(0xab7f);
ThreeWire_WriteMsb16Data(0xac7f);
ThreeWire_WriteMsb16Data(0xb0a0);
ThreeWire_WriteMsb16Data(0xb1a0);
ThreeWire_WriteMsb16Data(0xb2a0);
ThreeWire_WriteMsb16Data(0xb34e);
ThreeWire_WriteMsb16Data(0xb448);
ThreeWire_WriteMsb16Data(0xb52d);
ThreeWire_WriteMsb16Data(0xb625);
ThreeWire_WriteMsb16Data(0xb722);
ThreeWire_WriteMsb16Data(0xb81d);
ThreeWire_WriteMsb16Data(0xb91d);
ThreeWire_WriteMsb16Data(0xba14);
ThreeWire_WriteMsb16Data(0xbb70);
ThreeWire_WriteMsb16Data(0xbc03);
ThreeWire_WriteMsb16Data(0xbd3e);
ThreeWire_WriteMsb16Data(0xbe20);
ThreeWire_WriteMsb16Data(0xc0a0);
ThreeWire_WriteMsb16Data(0xc1a0);
ThreeWire_WriteMsb16Data(0xc2a0);
ThreeWire_WriteMsb16Data(0xc34e);
ThreeWire_WriteMsb16Data(0xc448);
ThreeWire_WriteMsb16Data(0xc52d);
ThreeWire_WriteMsb16Data(0xc625);
ThreeWire_WriteMsb16Data(0xc722);
ThreeWire_WriteMsb16Data(0xc81d);
ThreeWire_WriteMsb16Data(0xc91d);
ThreeWire_WriteMsb16Data(0xca14);
ThreeWire_WriteMsb16Data(0xcb70);
ThreeWire_WriteMsb16Data(0xcc03);
ThreeWire_WriteMsb16Data(0xcd3e);
ThreeWire_WriteMsb16Data(0xce20);
ThreeWire_WriteMsb16Data(0xd0a0);
ThreeWire_WriteMsb16Data(0xd1a0);
ThreeWire_WriteMsb16Data(0xd2a0);
ThreeWire_WriteMsb16Data(0xd34e);
ThreeWire_WriteMsb16Data(0xd448);
ThreeWire_WriteMsb16Data(0xd52d);
ThreeWire_WriteMsb16Data(0xd625);
ThreeWire_WriteMsb16Data(0xd722);
ThreeWire_WriteMsb16Data(0xd81d);
ThreeWire_WriteMsb16Data(0xd91d);
ThreeWire_WriteMsb16Data(0xda14);
ThreeWire_WriteMsb16Data(0xdb70);
ThreeWire_WriteMsb16Data(0xdc03);
ThreeWire_WriteMsb16Data(0xdd3e);
ThreeWire_WriteMsb16Data(0xde20);
ThreeWire_WriteMsb16Data(0x1101); //Set Normal Operation
// patch 5.2.1_33@mattwang@rename LC15004_write to ThreeWire_WriteMsb16Data end
//Add for Toppoly LTPS LCD end by Hamming@2003.04.30
XBYTE[0x201C] = 0x00; // using 27MHz for TV
XBYTE[0x2D00] = 0x04; // tvdspmode
XBYTE[0x2D08] = 0x7b; // vldx0
XBYTE[0x2D09] = 0x00; // vldx0
XBYTE[0x2D0A] = 0x14; // vldy0
XBYTE[0x2D0B] = 0x00; // vldy0
XBYTE[0x2D0C] = 0x24; // vldx1
XBYTE[0x2D0D] = 0x03; // vldx1
XBYTE[0x2D0E] = 0xff; // vldy1
XBYTE[0x2D0F] = 0x00; // vldy1
XBYTE[0x2D1B] = 0x00; // imgvofst
XBYTE[0x2D1C] = 0x00; // imgvofst
XBYTE[0x2D1D] = 0x00; // imghofst
XBYTE[0x2D1E] = 0x00; // imghofst
XBYTE[0x2D2A] = 0x03; // CCIR type //
XBYTE[0x2D21] = 0x20; // osdsubsamp
XBYTE[0x2D32] = 0x16; // osdvzoomfactor //Hamming@2003.04.30
XBYTE[0x2D33] = 0x02; // osdvofst //Hamming@2003.04.30
XBYTE[0x2D34] = 0x30; // osdhofst
//patch4.3@yichang@0613 for TV sharpness
//XBYTE[0x2DE2] = 0x01; // field mode
XBYTE[0x2DE2] = 0x03; // field mode
//patch4.4@yichang@tv out quality begin
chipID = XBYTE[0x20FF];
if(chipID < 2)
XBYTE[0x2D19] = 0x40;
else
XBYTE[0x2D19] = 0x3F;
//patch4.4@yichang@tv out quality end
status = 0;
}
//#endif
// patch 5.2.1_28@mattwang@rename CASIO2G to CASIO2G1181 beg
//#ifdef CASIO2G1181
if(index==18)// Casio2G1181 output
{
//Add for Casio 2G LCD begin by Hamming@2003.04.30
// patch 5.2.1_31@mattwang@fix CASIO2G panel power on sequence beg
XBYTE[0x2D76]|= 0x04; // set DIGTV18 as output to control POCB // 20040414 mattwang add
XBYTE[0x2D73]&= 0xFB; // set POCB low // 20040414 mattwang add
XBYTE[0x2D73]|= 0x04; // set POCB hogh // 20040414 mattwang add
// patch 5.2.1_33@mattwang@rename Casio2G_write to ThreeWire_WriteLsb12Data beg
ThreeWire_WriteLsb12Data(0x0086); // FUNC1: standby mode // 20040413 mattwang add
ThreeWire_WriteLsb12Data(0x0290); // BRIGHT
ThreeWire_WriteLsb12Data(0x06f1); // VCOMDC
ThreeWire_WriteLsb12Data(0x07f2); // CONTRAST/PANEL1
ThreeWire_WriteLsb12Data(0x0413); // VDISP/PANEL2
ThreeWire_WriteLsb12Data(0x0094); // HDISP
ThreeWire_WriteLsb12Data(0x07B5); // PANEL3
//ThreeWire_WriteLsb12Data(0x0186); // FUNC1 // 20040413 mattwang mark
ThreeWire_WriteLsb12Data(0x0037); // FUNC2
// patch 5.2.1_33@mattwang@rename Casio2G_write to ThreeWire_WriteLsb12Data end
// patch 5.2.1_31@mattwang@fix CASIO2G panel power on sequence end
XBYTE[0x2D26] = 0x00; // osdsubsamp //Added by Hamming
XBYTE[0x2D04] = 0xff; // hpixel
XBYTE[0x2D05] = 0x01; // hpixel
XBYTE[0x2D06] = 0x01; // vsyncw
XBYTE[0x2D07] = 0x02; // hsyncw
XBYTE[0x2D08] = 0x0b; // vldx0
XBYTE[0x2D09] = 0x00; // vldx0
XBYTE[0x2D0A] = 0x01; // vldy0
XBYTE[0x2D0B] = 0x00; // vldy0
XBYTE[0x2D0C] = 0xf2; // vldx1
XBYTE[0x2D0D] = 0x01; // vldx1
XBYTE[0x2D0E] = 0xef; // vldy1
XBYTE[0x2D0F] = 0x00; // vldy1
XBYTE[0x2D20] = 0x40; // imgsubsamp
XBYTE[0x2D21] = 0x40; // osdsubsamp
//Add for Casio 2G LCD end by Hamming@2003.04.30
XBYTE[0x201C] = 0x02; // using 24MHz for unipac TFT-LCD
XBYTE[0x2D00] = 0x08; // tvdspmode
XBYTE[0x2D02] = 0xf2; // vline
XBYTE[0x2D03] = 0x00; // vline
XBYTE[0x2D1B] = 0x00; // imgvofst
XBYTE[0x2D1C] = 0x00; // imgvofst
XBYTE[0x2D1D] = 0x00; // imghofst
XBYTE[0x2D1E] = 0x00; // imghofst
XBYTE[0x2D33] = 0x00; // osdvofst
XBYTE[0x2D34] = 0x1a; // osdhofst
//patch4.3@yichang@0613 for TV sharpness
//XBYTE[0x2DE2] = 0x00; // field mode
XBYTE[0x2DE2] = 0x02; // field mode
// patch 5.2.1_31@mattwang@fix CASIO2G panel power on sequence beg
// patch 5.2.1_33@mattwang@rename Casio2G_write to ThreeWire_WriteLsb12Data beg
ThreeWire_WriteLsb12Data(0x0186); // FUNC1: normal mode // 20040413 mattwang add
// patch 5.2.1_33@mattwang@rename Casio2G_write to ThreeWire_WriteLsb12Data end
status = 0;
// patch 5.2.1_31@mattwang@fix CASIO2G panel power on sequence end
}
//#endif
// patch 5.2.1_28@mattwang@rename CASIO2G to CASIO2G1181 end
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