📄 l2_cf.c
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}
else
{
return L2K_ERROR_GENERAL;
}
}
*Data = XBYTE[0x2430]; // read data
XBYTE[0x2439] = 0x01; // set regnn to high
//PRINT_L2(" L2_CFAttrMemRd: Exit L2_CFAttrMemRd(Hihg address=8'h%x,Low address=8'h%x,Data=8'h%x)\n",(USHORT)HighA,(USHORT)LowA,(USHORT)*Data);
return L2K_SUCCESS;
//patch4.5@ada@Add timeout count end
}
//-----------------------------------------------------------------------------
//L2_CFComMemWr (for Memory mode only)
//-----------------------------------------------------------------------------
/*
routine description:
CF card common memory write
(for Memory mode only)
arguments:
LowA: low address (Addr[2:0])
HighA: high address (Addr[10:3])
Data
return value:
0x00 - success
others - error
*/
UCHAR L2_CFComMemWr(UCHAR HighA,UCHAR LowA,UCHAR Data) USING_0
{
//patch4.5@ada@Add timeout count begin
USHORT timeout_count = 0xffff;
//PRINT_L2(" L2_CFComMemWr: Enter L2_CFComMemWr\n");
XBYTE[0x2432] = LowA;
XBYTE[0x2433] = HighA;
XBYTE[0x2430] = Data; // write data
while(XBYTE[0x243B]==0) // wait for ready
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return L2K_ERROR_GENERAL;
}
}
//PRINT_L2(" L2_CFComMemWr: Exit L2_CFComMemWr(Hihg address=8'h%x,Low address=8'h%x,Data=8'h%x)\n",(USHORT)HighA,(USHORT)LowA,(USHORT)Data);
return L2K_SUCCESS;
//patch4.5@ada@Add timeout count end
}
//-----------------------------------------------------------------------------
//L2_CFComMemRd (for Memory mode only)
//-----------------------------------------------------------------------------
/*
routine description:
CF card common memory read
(for Memory mode only)
arguments:
LowA: low address (Addr[2:0])
HighA: high address (Addr[10:3])
Data
return value:
0x00 - success
others - error
*/
UCHAR L2_CFComMemRd(UCHAR HighA,UCHAR LowA,UCHAR* Data) USING_0
{
//patch4.5@ada@Add timeout count begin
USHORT timeout_count = 0xffff;
//PRINT_L2(" L2_CFComMemRd: Enter L2_CFComMemRd\n");
XBYTE[0x2434] = 0x06; // prefetch byte access
XBYTE[0x2432] = LowA;
XBYTE[0x2433] = HighA;
*Data = XBYTE[0x2430]; // dummy read pulse
XBYTE[0x2434] = 0x04; // disable prefetch
while(XBYTE[0x243B]==0) // wait for ready
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return L2K_ERROR_GENERAL;
}
}
*Data = XBYTE[0x2430]; // read data
//PRINT_L2(" L2_CFComMemRd: Exit L2_CFComMemRd(Hihg address=8'h%x,Low address=8'h%x,Data=8'h%x)\n",(USHORT)HighA,(USHORT)LowA,(USHORT)*Data);
return L2K_SUCCESS;
//patch4.5@ada@Add timeout count end
}
#endif
#if (CFAIDE)
//-----------------------------------------------------------------------------
//L2_CFCheckIRQ (for True IDE mode only)
//-----------------------------------------------------------------------------
/*
routine description:
Check the CF card IRQ pin (for True IDE mode only)
arguments:
ClearIRQ : 0 nothing
1 clear the IRQ flag
IRQ : 0 IRQ pin is low
1 IRQ pin is high
return value:
None
*/
void L2_CFCheckIRQ(UCHAR ClearIRQ,UCHAR* IRQ) USING_0
{
//PRINT_L2(" L2_CFCheckIRQ: Enter L2_CFCheckIRQ\n");
if(ClearIRQ) XBYTE[0x24C0] = 0x00;
*IRQ = XBYTE[0x24C0];
//PRINT_L2(" L2_CFCheckIRQ: Exit L2_CFCheckIRQ\n");
}
//-----------------------------------------------------------------------------
//L2_CFSetCsA (for True IDE mode only)
//-----------------------------------------------------------------------------
/*
routine description:
Set the CF card Cs & Addr[2:0] (for True IDE mode only)
arguments:
CsA:
[0]: Addr[0]
[1]: Addr[1]
[2]: Addr[2]
[3]: Cs[0]
[4]: Cs[1]
return value:
0x00 - success
others - error
*/
UCHAR L2_CFSetCsA(UCHAR CsA) USING_0
{
UCHAR tmp0,tmp1;
//PRINT_L2(" L2_CFSetCsA: Enter L2_CFSetCsA\n");
tmp0 = CsA&0x07;
XBYTE[0x2432] = tmp0;
tmp1 = (CsA&0x18)>>3;
XBYTE[0x2436] = tmp1;
//PRINT_L2(" L2_CFSetCsA: Exit L2_CFSetCsA(Cs=8'h%x,Addr=8'h%x)\n",(USHORT)tmp1,(USHORT)tmp0);
return L2K_SUCCESS;
}
//-----------------------------------------------------------------------------
//L2_CFSetWordCsAWr (for True IDE mode)
//-----------------------------------------------------------------------------
/*
routine description:
Set the CF card Cs/Addr[2:0] and then write a word to the data bus (for True IDE mode only)
arguments:
CsA:
[0]: Addr[0]
[1]: Addr[1]
[2]: Addr[2]
[3]: Cs[0]
[4]: Cs[1]
Data: write data
return value:
0x00 - success
others - error
*/
UCHAR L2_CFSetWordCsAWr(UCHAR CsA, USHORT Data) USING_0
{
UCHAR tmp0,tmp1;
//PRINT_L2(" L2_CFSetWordCsAWr: Enter L2_CFSetWordCsAWr\n");
tmp0 = CsA&0x07;
XBYTE[0x2432] = tmp0;
tmp1 = (CsA&0x18)>>3;
XBYTE[0x2436] = tmp1;
XBYTE[0x2430] = (UCHAR)Data&0xff;
XBYTE[0x2431] = (UCHAR)(Data>>8)&0xff;
//PRINT_L2(" L2_CFSetWordCsAWr: Exit L2_CFSetWordCsAWr(Cs=8'h%x,Addr=8'h%x,Data=16'h%x)\n",(USHORT)tmp1,(USHORT)tmp0,Data);
return L2K_SUCCESS;
}
//-----------------------------------------------------------------------------
//L2_CFSetWordCsARd (for True IDE mode only)
//-----------------------------------------------------------------------------
/*
routine description:
Set the CF card Cs/Addr[2:0] and then read a word from the data bus (for True IDE mode only)
arguments:
CsA:
[0]: Addr[0]
[1]: Addr[1]
[2]: Addr[2]
[3]: Cs[0]
[4]: Cs[1]
Data: read data
return value:
0x00 - success
others - error
*/
UCHAR L2_CFSetWordCsARd(UCHAR CsA, USHORT* Data) USING_0
{
UCHAR tmp0,tmp1,tmp2,tmp3;
//patch4.5@ada@Add timeout count begin
USHORT timeout_count = 0xffff;
//PRINT_L2(" L2_CFSetWordCsARd: Enter L2_CFSetWordCsARd\n");
tmp0 = CsA&0x07;
XBYTE[0x2432] = tmp0;
tmp1 = (CsA&0x18)>>3;
XBYTE[0x2436] = tmp1;
XBYTE[0x2434] = 0x0b; // turn on prefetch to send read-pulse
tmp2 = XBYTE[0x2431]; // dummy read for trigger read-pulse
XBYTE[0x2434] = 0x09; // turn off prefetch to read previous data
while(XBYTE[0x243B]==0) // wait chip ready
{
if (timeout_count > 0)
{
timeout_count--;
}
else
{
return L2K_ERROR_GENERAL;
}
}
tmp2 = XBYTE[0x2430];
//patch4.5@ada@Fix access status register in word unit bug begin
if (CsA == 0x10)
{
tmp3 = XBYTE[0x2431];
}
else
{
tmp3 = 0x00;
}
//tmp3 = XBYTE[0x2431];
//patch4.5@ada@Fix access status register in word unit bug begin
*Data = (tmp3<<8)|(tmp2);
//PRINT_L2(" L2_CFSetWordCsARd: Exit L2_CFSetWordCsARd(Cs=8'h%x,Addr=8'h%x,Data=16'h%x)\n",(USHORT)tmp1,(USHORT)tmp0,*Data);
return L2K_SUCCESS;
//patch4.5@ada@Add timeout count end
}
#endif
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