l2_cpu.c

台湾凌阳方案300万数码相机源代码

/*++

Copyright (c) 2001 Sunplus Technology Co., Ltd.

Module Name:

        L2_cpu.c

Abstract:

        Module related to L2 CPU functions

Environment:

        Keil C51 Compiler

Revision History:

        11/12/2001      WZH    created

--*/
//=============================================================================
//Header file
//=============================================================================
#include "general.h"

//Joe@2003.3.19 20:36 add begin
#include "JoeToEvb.h"
//Joe@2003.3.19 20:36 add end
//=============================================================================
//Symbol
//=============================================================================
//-----------------------------------------------------------------------------
//Constant
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
//Variable
//-----------------------------------------------------------------------------
sfr RamPage = 0x9B;
sfr MemStretch = 0x8E;

//=============================================================================
//Program
//=============================================================================

//-----------------------------------------------------------------------------
//L2_InitCPU
//-----------------------------------------------------------------------------
/*
routine description:
        cpu interface hardware initialization
arguments:
        CamMode: camera operation mode
return value:
        0x00   - success
        others - error
*/
UCHAR L2_InitCPU(UCHAR CamMode) USING_0
{
        //PRINT_L2("        L2_InitCPU: Enter L2_InitCPU\n");

        if(CamMode > 6) return 0x01;

        if(CamMode == 0)
        {
                MemStretch = 0x00;                        // memory stretch = 0
                XBYTE[0x2C00] = 0x0F;                     // rampageen, rompageen, SRAM enable
                XBYTE[0x2024] = 0x01;                     // CPU clock

                //Joe@2003.3.14 20:55 modify begin
                /*
                if(L2K_CPUInternal == 1)
                {
                        XBYTE[0x2C02] = L2K_P1OE;               // P1 & P3 are always drive
                        XBYTE[0x2C03] = L2K_P3OE;
                        //P1 = 0xff;
                        P3 = 0xff;
                }
                else
                {
                        XBYTE[0x2C02] = 0x00;
                        XBYTE[0x2C03] = 0x00;
                }
                if(L2K_CPUP1 == 1)
                        XBYTE[0x201A] = (XBYTE[0X201A] & 0x0f); // P1 is used for GPIO
                else
                        XBYTE[0x201A] = (XBYTE[0X201A] | 0x10);
		*/
		UI_SetCPUPort();
		//Joe@2003.3.14 20:55 modify end

                RamPage = 0x00;
        }

        //PRINT_L2("        L2_InitCPU: Exit L2_InitCPU\n");

        return L2K_SUCCESS;
}

//-----------------------------------------------------------------------------
//L2_Set4KSRAMMode
//-----------------------------------------------------------------------------
/*
routine description:
        high bank 4k sram mode selection
arguments:
        Mode: 0: addressible SRAM (0x1000 - 0x1FFF)
              1: access data port (0x2C10) (0x0000 - 0x0FFF)
              2: used for DMA buffer (0x0000 - 0x0FFF)
return value:
        0x00   - success
        others - error
*/
UCHAR L2_Set4KSRAMMode(UCHAR Mode) USING_0
{
        UCHAR tmp0;
        tmp0 = XBYTE[0x2C00];
        XBYTE[0x2C00] = tmp0 & 0x1d;

        //PRINT_L2("        L2_Set4KSRAMMode: Enter L2_Set4KSRAMMode\n");

        if(Mode == 0)        XBYTE[0x2C11] = 0x00;
	else if(Mode == 1)   XBYTE[0x2C11] = 0x01;
	else if(Mode == 2)   XBYTE[0x2C11] = 0x02;
	else                {XBYTE[0x2C00] = tmp0 | 0x02; return 0x01;}

	XBYTE[0x2C00] = tmp0 | 0x02;

        //PRINT_L2("        L2_Set4KSRAMMode: Exit L2_Set4KSRAMMode\n");

        return L2K_SUCCESS;
}

//-----------------------------------------------------------------------------
//L2_4KSRAMBufIdx
//-----------------------------------------------------------------------------
/*
routine description:
        4k sram buffer index management
arguments:
        Mode: 0: read the buffer input index & buffer output index
              1: Set start index (from 0x0000 - 0x0FFF)
        StartIdx: 4K buffer start index
        InIdx : 4K buffer input index
        OutIdx : 4K buffer output index
return value:
        0x00   - success
        others - error
*/
UCHAR L2_4KSRAMBufIdx(UCHAR Mode, USHORT StartIdx, USHORT* InIdx, USHORT* OutIdx) USING_0
{
        UCHAR tmp0;
        tmp0 = XBYTE[0x2C11];

        //PRINT_L2("        L2_4KSRAMBufIdx: Enter L2_4KSRAMBufIdx\n");
        if(Mode!=0)
        {
                XBYTE[0x2C12] = (UCHAR)StartIdx&0xFF;
                XBYTE[0x2C13] = (UCHAR)(StartIdx>>8)&0x0F;
                XBYTE[0x2C11] = 0x04;
                XBYTE[0x2C11] = tmp0;
        }
        *InIdx   = (USHORT)XBYTE[0x2CA0];
        *InIdx  |= (USHORT)XBYTE[0x2CA1]<<8;
        *OutIdx  = (USHORT)XBYTE[0x2CA2];
        *OutIdx |= (USHORT)XBYTE[0x2CA3]<<8;

        //PRINT_L2("        L2_4KSRAMBufIdx: Exit L2_4KSRAMBufIdx\n");

        return L2K_SUCCESS;
}

//-----------------------------------------------------------------------------
//L2_Write4KSRAMPort
//-----------------------------------------------------------------------------
/*
routine description:
        Write 4K SRAM port
arguments:
        Data: write data
return value:
        None
*/
void L2_Write4KSRAMPort(UCHAR Data) USING_0
{
        //PRINT_L2("        L2_Write4KSRAMPort: Enter L2_Write4KSRAMPort\n");

        XBYTE[0x2C10] = Data;

        //PRINT_L2("        L2_Write4KSRAMPort: Exit L2_Write4KSRAMPort\n");
}

//-----------------------------------------------------------------------------
//L2_Read4KSRAMPort
//-----------------------------------------------------------------------------
/*
routine description:
        Read 4K SRAM port
arguments:
        Data: read data
return value:
        None
*/
void L2_Read4KSRAMPort(UCHAR* Data) USING_0
{
        //PRINT_L2("        L2_Read4KSRAMPort: Enter L2_Read4KSRAMPort\n");

        *Data = XBYTE[0x2C10];

        //PRINT_L2("        L2_Read4KSRAMPort: Exit L2_Read4KSRAMPort\n");
}

//-----------------------------------------------------------------------------
//L2_DownloadROM
//-----------------------------------------------------------------------------
/*
routine description:
        download data from external ROM to 4K SRAM
arguments:
        Addr: 4K SRAM write address
        ROMAddr: external ROM read address
        nByte: the number of byte to be transfer   // maximum size is 4K bytes
return value:
        0x00   - success
        others - error
Note: cross page is not available to reduce the dummy coding time
*/
UCHAR L2_DownloadROM(USHORT SRAMAddr, ULONG ROMAddr, USHORT nByte) USING_0
{
        USHORT srcend;
	USHORT i, romaddrl;
	UCHAR  tmp0;

        //PRINT_L2("        L2_DownloadROM: Enter L2_DownloadROM(Addr=%x,ROMAddr=%lx,nByte=%x)\n",SRAMAddr,ROMAddr,(USHORT)nByte);

        romaddrl = ROMAddr & 0x00007FFF ;
        RamPage  = (ROMAddr & 0x000F8000) >> 15;

	srcend = nByte + 0x8000;

        if((SRAMAddr & 0xF000)!=0) return 0x01;

        XBYTE[0x2C12] = (SRAMAddr & 0x00FF);
        XBYTE[0x2C13] = (SRAMAddr & 0x0F00) >> 8;

        tmp0 = XBYTE[0x2C00];
        XBYTE[0x2C00] = tmp0 & 0x1d;
        XBYTE[0x2C11] = 0x06;
        XBYTE[0x2C11] = 0x01;
        XBYTE[0x2C00] = tmp0 | 0x02;

        for(i=0x8000 ; i<srcend ; i++)
        {
                XBYTE[0x2C10] = XBYTE[romaddrl+i];
        }

        //PRINT_L2("        L2_DownloadROM: Exit L2_DownloadROM\n");

        return L2K_SUCCESS;

}

#ifdef TestModeEn
//-----------------------------------------------------------------------------
//L2_TestCPU
//-----------------------------------------------------------------------------
/*
routine description:
        CPU module test.
arguments:
        TestLevel: the level of test
return value:
        0x00   - success
        others - error
*/
UCHAR L2_TestCPU(UCHAR TestLevel) USING_0
{
        data UCHAR  level;
        data UCHAR  error;
        data UCHAR  tmp0;
        data USHORT tmp1;

        level = TestLevel;
        error = 0;

        // CPU SRAM
        if((level==0) || (level==2))
        {
                tmp0 = XBYTE[0x2C00] ;
                XBYTE[0x2C00] |= 0x03;

                //test read/write sequence data
                for(tmp1=0; tmp1<0x2000; tmp1++)
                        XBYTE[tmp1] = (UCHAR)tmp1;
                for(tmp1=0; tmp1<0x2000; tmp1++)
                if(XBYTE[tmp1]!=(UCHAR)tmp1)
                        error = 1;

                //test 0x00->0xFF
                for(tmp1=0; tmp1<0x2000; tmp1++)
                        XBYTE[tmp1] = 0xFF;
                for(tmp1=0; tmp1<0x2000; tmp1++)
                        if(XBYTE[tmp1]!=0xFF)
                                error = 1;

                //test 0xFF->0x00