📄 l2_fssc.c
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#include "general.h"UCHAR L2_WriteSSC (UCHAR *RegAddr, UCHAR *RegData, UCHAR Count, UCHAR Option) USING_0{ UCHAR burst, sync, temp[1]; UCHAR i, j; if ((Count >= 16) | (Count == 0)) return 1; burst = (Option & 0x02) >> 1; sync = Option & 0x01; while (XBYTE[0X29A0] == 0x01) {;} // Wait is the serial interface is busy XBYTE[0X2901] = burst; // Select Sequential/Burst mode XBYTE[0X2903] = sync; // synchronize with Vd or not XBYTE[0X2905] = Count; // Set the number of bytes to transfer if (burst) { for (i=0;i < Count;i++) { j = 2*i; XBYTE[0X2910+j] = RegAddr[i]; // Set Register address XBYTE[0x2911+j] = RegData[i]; // Set data Register } } else { XBYTE[0X2910] = RegAddr[0]; // Set Register address for (i=0;i < Count;i++) { j = 2*i; XBYTE[0x2911+j] = RegData[i]; // Set data Register // L2_ReadSSC(RegAddr[0], temp, 0x01, 0x01); } }#ifdef YM3170 while (XBYTE[0X29A0] == 0x01) {;} // Wait is the serial interface is busy#endif return 0; }/////////////////////////////////////////////////////////////////////////////////////////////////UCHAR L2_ReadSSC(UCHAR RegAddr, UCHAR *RegData, UCHAR Count, UCHAR Option) USING_0{ UCHAR sync, subaddren, restarten, temp; UCHAR i, j; if ((Count >= 16) | (Count == 0)) return 1; subaddren = Option & 0x01; restarten = Option & 0x02; sync = Option & 0x04; while (XBYTE[0X29A0] == 0x01); //Wait is the serial interface is busy XBYTE[0X2901] = 0x00; // Select Sequential mode XBYTE[0X2903] = sync >> 2; // Synchronize with Vd or not XBYTE[0X2905] = Count << 4; // Set the number of bytes to Read XBYTE[0X2910] = RegAddr; // Set the address to read temp = 0x10 | (Option & 0x03); XBYTE[0X2902] = temp; //Set Prefetch while (XBYTE[0X29A0] == 0x01); //Wait is the serial interface is busy for (i = 0; i < Count; i++) { j = 2*i; RegData[i] = XBYTE[0X2911+j]; } return 0; }/////////////////////////////////////////////////////////////////////////////////////////////////#ifdef ICM107BUCHAR L2_WSSC107 (UCHAR *RegAddr, UCHAR *RegData, UCHAR Count, UCHAR Option) USING_0{ UCHAR sync; UCHAR k; sync = Option & 0x01; k = Count; while (XBYTE[0X29A0] == 0x01) {;} // Wait when the serial interface is busy XBYTE[0X2901] = 0; // Select Sequential XBYTE[0X2903] = sync; // synchronize with Vd or not XBYTE[0X2905] = 1; // Set the number of bytes to transfer XBYTE[0X2910] = RegAddr[0]; // Set Register address XBYTE[0x2911] = RegData[0]; // Set data Register return 0; }UCHAR L3_WaitUpdate107(void) USING_0{ UCHAR i, j, k, temp[1]; for (i = 0; i <255; i++) { for(j=0; j<5; j++) for(k=0; k<200; k++); L2_ReadSSC(0x00, temp, 0x01, 0x01); if ((i == 254) & ((temp[0] & 0x84) != 0x00)) { //PRINT_FRONT (" Check Failure, Read Reg 0x00 = %bx \n",temp[0]); } else if ((temp[0] & 0x84) == 0x00) { //PRINT_FRONT (" Check OK, Read Reg 0x00 = %bx \n", temp[0]); break; } } return 0;}#endif#ifdef ICM108UCHAR L2_WSSC108 (UCHAR *RegAddr, UCHAR *RegData, UCHAR Count, UCHAR Option) USING_0{ UCHAR sync; UCHAR k; sync = Option & 0x01; k = Count; while (XBYTE[0X29A0] == 0x01) {;} // Wait when the serial interface is busy XBYTE[0X2901] = 0; // Select Sequential XBYTE[0X2903] = sync; // synchronize with Vd or not XBYTE[0X2905] = 1; // Set the number of bytes to transfer XBYTE[0X2910] = RegAddr[0]; // Set Register address XBYTE[0x2911] = RegData[0]; // Set data Register return 0; }UCHAR L3_WaitUpdate108(void) USING_0{ UCHAR i, j, k, temp[1]; for (i = 0; i <255; i++) { for(j=0; j<5; j++) for(k=0; k<200; k++);//UCHAR L2_ReadSSC(UCHAR RegAddr, UCHAR *RegData, UCHAR Count, UCHAR Option) L2_ReadSSC(0x00, temp, 0x01, 0x01); if ((i == 254) & ((temp[0] & 0x84) != 0x00)) { //PRINT_FRONT (" Check Failure, Read Reg 0x00 = %bx \n",temp[0]); } else if ((temp[0] & 0x84) == 0x00) { //PRINT_FRONT (" Check OK, Read Reg 0x00 = %bx \n", temp[0]); break; } } return 0;}#endif//patch4.4@andrew@ICM109#ifdef ICM109UCHAR L2_WSSC109 (UCHAR *RegAddr, UCHAR *RegData, UCHAR Count, UCHAR Option) USING_0{ UCHAR sync; UCHAR k; sync = Option & 0x01; k = Count; while (XBYTE[0X29A0] == 0x01) {;} // Wait when the serial interface is busy XBYTE[0X2901] = 0; // Select Sequential XBYTE[0X2903] = sync; // synchronize with Vd or not XBYTE[0X2905] = 1; // Set the number of bytes to transfer XBYTE[0X2910] = RegAddr[0]; // Set Register address XBYTE[0x2911] = RegData[0]; // Set data Register return 0; }UCHAR L3_WaitUpdate109(void) USING_0{ UCHAR i, j, k, temp[1]; for (i = 0; i <255; i++) { for(j=0; j<5; j++) for(k=0; k<200; k++);//UCHAR L2_ReadSSC(UCHAR RegAddr, UCHAR *RegData, UCHAR Count, UCHAR Option) L2_ReadSSC(0x00, temp, 0x01, 0x01); if ((i == 254) & ((temp[0] & 0x84) != 0x00)) { //PRINT_FRONT (" Check Failure, Read Reg 0x00 = %bx \n",temp[0]); } else if ((temp[0] & 0x84) == 0x00) { //PRINT_FRONT (" Check OK, Read Reg 0x00 = %bx \n", temp[0]); break; } } return 0;}#endif
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