📄 os_viewc.lst
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125
126
127 #if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */
128 OS_CPU_SR cpu_sr = 0;
\ 00000008 0000A0E3 MOV R0,#+0
\ 0000000C 00B0B0E1 MOVS R11,R0
129 #endif
130
131
132 OSView_TmrInit(); /* Initialize the free running timer */
\ 00000010 ........ _BLF OSView_TmrInit,??OSView_TmrInit??rA
133
134 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_0
135 /* Compute divisor for desired baud rate */
136 p_clk_freq = BSP_CPU_PclkFreq(PCLK_UART0); /* Get the CPU clock frequency */
137
138 div = (INT16U)(((2 * p_clk_freq / 16 / baud_rate) + 1) / 2);
139 divlo = div & 0x00FF; /* Split divisor into LOW and HIGH bytes */
140 divhi = (div >> 8) & 0x00FF;
141 lcr = 0x03; /* 8 Bits, 1 Stop, No Parity */
142
143 OS_ENTER_CRITICAL();
144 /* Configure P0.2 & P0.3 for UART0 */
145 pinsel = PINSEL0;
146 pinsel &= 0xFFFFFF0F;
147 pinsel |= 0x00000050;
148 PINSEL0 = pinsel;
149
150 U0LCR = DEF_BIT_07; /* Set divisor access bit */
151 U0DLL = divlo; /* Load divisor */
152 U0DLM = divhi;
153 U0LCR = lcr; /* Set line control register (Bit 8 is 0) */
154 U0IER = 0x00; /* Disable both Rx and Tx interrupts */
155 U0FCR = 0x07; /* Enable FIFO, flush Rx & Tx */
156 OS_EXIT_CRITICAL();
157 /* VIC UART #1 Initialization */
158 VICIntSelect &= ~(1 << VIC_UART0); /* Enable interrupts */
159 VICVectAddr6 = (INT32U)OSView_RxTxISRHandler; /* Set the vector address */
160 VICIntEnable = (1 << VIC_UART0); /* Enable Interrupts */
161 #endif
162
163
164
165 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_1
166 /* Compute divisor for desired baud rate */
167 p_clk_freq = BSP_CPU_PclkFreq(PCLK_UART1); /* Get the CPU clock frequency */
\ 00000014 0400A0E3 MOV R0,#+4
\ 00000018 ........ _BLF BSP_CPU_PclkFreq,??BSP_CPU_PclkFreq??rA
\ 0000001C 0090B0E1 MOVS R9,R0
168
169 div = (INT16U)(((2 * p_clk_freq / 16 / baud_rate) + 1) / 2);
\ 00000020 0200A0E3 MOV R0,#+2
\ 00000024 900911E0 MULS R1,R0,R9
\ 00000028 2102B0E1 LSRS R0,R1,#+4
\ 0000002C 0410B0E1 MOVS R1,R4
\ 00000030 ........ _BLF ??divu32_a,??rA??divu32_a
\ 00000034 010091E2 ADDS R0,R1,#+1
\ 00000038 A000B0E1 LSRS R0,R0,#+1
\ 0000003C 0050B0E1 MOVS R5,R0
170 divlo = div & 0x00FF; /* Split divisor into LOW and HIGH bytes */
\ 00000040 0500B0E1 MOVS R0,R5
\ 00000044 0060B0E1 MOVS R6,R0
171 divhi = (div >> 8) & 0x00FF;
\ 00000048 2504B0E1 LSRS R0,R5,#+8
\ 0000004C 0070B0E1 MOVS R7,R0
172 lcr = 0x03; /* 8 Bits, 1 Stop, No Parity */
\ 00000050 0300A0E3 MOV R0,#+3
\ 00000054 0080B0E1 MOVS R8,R0
173
174 OS_ENTER_CRITICAL();
\ 00000058 ........ _BLF OS_CPU_SR_Save,??OS_CPU_SR_Save??rA
\ 0000005C 00B0B0E1 MOVS R11,R0
175 /* Configure P3.16 & P3.17 for UART1 */
176 pinsel = PINSEL7;
\ 00000060 8C009FE5 LDR R0,??OSView_InitTarget_0 ;; 0xffffffffe002c01c
\ 00000064 000090E5 LDR R0,[R0, #+0]
\ 00000068 00A0B0E1 MOVS R10,R0
177 pinsel &= 0xFFFFFFF0;
\ 0000006C 0FA0DAE3 BICS R10,R10,#0xF
178 pinsel |= 0x0000000F;
\ 00000070 0FA09AE3 ORRS R10,R10,#0xF
179 PINSEL7 = pinsel;
\ 00000074 78009FE5 LDR R0,??OSView_InitTarget_0 ;; 0xffffffffe002c01c
\ 00000078 00A080E5 STR R10,[R0, #+0]
180
181 U1LCR = DEF_BIT_07; /* Set divisor access bit */
\ 0000007C CE02A0E3 MOV R0,#-536870900
\ 00000080 400B80E3 ORR R0,R0,#0x10000
\ 00000084 8010A0E3 MOV R1,#+128
\ 00000088 0010C0E5 STRB R1,[R0, #+0]
182 U1DLL = divlo; /* Load divisor */
\ 0000008C E004A0E3 MOV R0,#-536870912
\ 00000090 400B80E3 ORR R0,R0,#0x10000
\ 00000094 0060C0E5 STRB R6,[R0, #+0]
183 U1DLM = divhi;
\ 00000098 4E02A0E3 MOV R0,#-536870908
\ 0000009C 400B80E3 ORR R0,R0,#0x10000
\ 000000A0 0710B0E1 MOVS R1,R7
\ 000000A4 FF1011E2 ANDS R1,R1,#0xFF ;; Zero extend
\ 000000A8 001080E5 STR R1,[R0, #+0]
184 U1LCR = lcr; /* Set line control register (Bit 8 is 0) */
\ 000000AC CE02A0E3 MOV R0,#-536870900
\ 000000B0 400B80E3 ORR R0,R0,#0x10000
\ 000000B4 0080C0E5 STRB R8,[R0, #+0]
185 U1IER = 0x00; /* Disable both Rx and Tx interrupts */
\ 000000B8 4E02A0E3 MOV R0,#-536870908
\ 000000BC 400B80E3 ORR R0,R0,#0x10000
\ 000000C0 0010A0E3 MOV R1,#+0
\ 000000C4 001080E5 STR R1,[R0, #+0]
186 U1FCR = 0x07; /* Enable FIFO, flush Rx & Tx */
\ 000000C8 8E02A0E3 MOV R0,#-536870904
\ 000000CC 400B80E3 ORR R0,R0,#0x10000
\ 000000D0 0710A0E3 MOV R1,#+7
\ 000000D4 001080E5 STR R1,[R0, #+0]
187 OS_EXIT_CRITICAL();
\ 000000D8 0B00B0E1 MOVS R0,R11
\ 000000DC ........ _BLF OS_CPU_SR_Restore,??OS_CPU_SR_Restore??rA
188 /* VIC UART #1 Initialization */
189 // VICIntSelect &= ~(1 << VIC_UART1); /* Enable interrupts */
190 VICVectAddr7 = (INT32U)OSView_RxTxISRHandler; /* Set the vector address */
\ 000000E0 E300E0E3 MVN R0,#+227
\ 000000E4 E00EC0E3 BIC R0,R0,#0xE00
\ 000000E8 08109FE5 LDR R1,??OSView_InitTarget_0+0x4 ;; OSView_RxTxISRHandler
\ 000000EC 001080E5 STR R1,[R0, #+0]
191 // VICIntEnable = (1 << VIC_UART1); /* Enable Interrupts */
192 #endif
193 }
\ 000000F0 F08FBDE8 POP {R4-R11,PC} ;; return
\ ??OSView_InitTarget_0:
\ 000000F4 1CC002E0 DC32 0xffffffffe002c01c
\ 000000F8 ........ DC32 OSView_RxTxISRHandler
194
195 /*
196 *********************************************************************************************************
197 * Disable & Enable Rx Interrupts
198 *
199 * Description: These functions enable and disable the Rx interrupt.
200 *
201 * Arguments : none
202 *
203 * Returns : none
204 *********************************************************************************************************
205 */
206
\ In segment CODE, align 4, keep-with-next
207 void OSView_RxIntDis (void)
208 {
209 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_0
210 U0IER = 0;
211 #endif
212
213 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_1
214 U1IER = 0;
\ OSView_RxIntDis:
\ 00000000 4E02A0E3 MOV R0,#-536870908
\ 00000004 400B80E3 ORR R0,R0,#0x10000
\ 00000008 0010A0E3 MOV R1,#+0
\ 0000000C 001080E5 STR R1,[R0, #+0]
215 #endif
216 }
\ 00000010 0EF0A0E1 MOV PC,LR ;; return
217
\ In segment CODE, align 4, keep-with-next
218 void OSView_RxIntEn (void)
219 {
220 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_0
221 U0IER = DEF_BIT_00;
222 #endif
223
224 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_1
225 U1IER = DEF_BIT_00;
\ OSView_RxIntEn:
\ 00000000 4E02A0E3 MOV R0,#-536870908
\ 00000004 400B80E3 ORR R0,R0,#0x10000
\ 00000008 0110A0E3 MOV R1,#+1
\ 0000000C 001080E5 STR R1,[R0, #+0]
226 #endif
227 }
\ 00000010 0EF0A0E1 MOV PC,LR ;; return
228
229 /*
230 *********************************************************************************************************
231 * Rx & Tx Communication handler for uC/OS-View
232 *
233 * Note(s) : This adaptation of uC/OS-View assumes that a 'combined' interrupt is generated by the UART
234 * and thus these functions need not be populated.
235 *********************************************************************************************************
236 */
237
\ In segment CODE, align 4, keep-with-next
238 void OSView_RxISRHandler (void)
239 {
240 ;
241 }
\ OSView_RxISRHandler:
\ 00000000 0EF0A0E1 MOV PC,LR ;; return
242
\ In segment CODE, align 4, keep-with-next
243 void OSView_TxISRHandler (void)
244 {
245 ;
246 }
\ OSView_TxISRHandler:
\ 00000000 0EF0A0E1 MOV PC,LR ;; return
247
248
249 /*
250 *********************************************************************************************************
251 * Rx/Tx Communication handler for uC/OS-View ('combined' interrupt handler)
252 *
253 * Description: The Rx/Tx ISR handler.
254 *
255 * Arguments : none.
256 *
257 * Returns : none
258 *********************************************************************************************************
259 */
260
\ In segment CODE, align 4, keep-with-next
261 void OSView_RxTxISRHandler (void)
262 {
\ OSView_RxTxISRHandler:
\ 00000000 00402DE9 PUSH {LR}
\ 00000004 04D04DE2 SUB SP,SP,#+4
263 volatile INT8U rx_data;
264 volatile INT8U lsr;
265 volatile INT8U iir;
266
267
268 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_0
269 iir = U0IIR & 0x0F;
270 while (iir != 1) {
271 switch (iir) {
272 case 0: /* Modem interrupt? */
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