📄 bsp.lst
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328 }
329
330 case PCLK_BAT_RAM:
331 case PCLK_GPIO:
332 case PCLK_PCB:
333 case PCLK_I2C1:
334 case PCLK_SSP0:
335 case PCLK_TIMER2:
336 case PCLK_TIMER3:
337 case PCLK_UART2:
338 case PCLK_UART3:
339 case PCLK_I2C2:
340 case PCLK_MCI:
341 case PCLK_SYSCON:
342 selection = ((PCLKSEL1 >> ((pclk - 16) * 2)) & 0x03);
\ ??BSP_CPU_PclkFreq_8:
\ 0000009C 5C009FE5 LDR R0,??BSP_CPU_PclkFreq_3+0x4 ;; 0xffffffffe01fc1ac
\ 000000A0 000090E5 LDR R0,[R0, #+0]
\ 000000A4 F01094E2 ADDS R1,R4,#+240
\ 000000A8 0220A0E3 MOV R2,#+2
\ 000000AC 920111E0 MULS R1,R2,R1
\ 000000B0 0320A0E3 MOV R2,#+3
\ 000000B4 300112E0 ANDS R0,R2,R0, LSR R1
\ 000000B8 0060B0E1 MOVS R6,R0
343 if (selection == 0) {
\ 000000BC 000056E3 CMP R6,#+0
\ 000000C0 0100001A BNE ??BSP_CPU_PclkFreq_9
344 return (clk_freq / 4);
\ 000000C4 2501B0E1 LSRS R0,R5,#+2
\ 000000C8 0A0000EA B ??BSP_CPU_PclkFreq_5
345 } else if (selection == 1) {
\ ??BSP_CPU_PclkFreq_9:
\ 000000CC 010056E3 CMP R6,#+1
\ 000000D0 0100001A BNE ??BSP_CPU_PclkFreq_10
346 return (clk_freq);
\ 000000D4 0500B0E1 MOVS R0,R5
\ 000000D8 060000EA B ??BSP_CPU_PclkFreq_5
347 } else if (selection == 2) {
\ ??BSP_CPU_PclkFreq_10:
\ 000000DC 020056E3 CMP R6,#+2
\ 000000E0 0100001A BNE ??BSP_CPU_PclkFreq_11
348 return (clk_freq / 2);
\ 000000E4 A500B0E1 LSRS R0,R5,#+1
\ 000000E8 020000EA B ??BSP_CPU_PclkFreq_5
349 } else {
350 return (clk_freq / 8);
\ ??BSP_CPU_PclkFreq_11:
\ 000000EC A501B0E1 LSRS R0,R5,#+3
\ 000000F0 000000EA B ??BSP_CPU_PclkFreq_5
351 }
352
353 default:
354 return (0);
\ ??BSP_CPU_PclkFreq_1:
\ 000000F4 0000A0E3 MOV R0,#+0
\ ??BSP_CPU_PclkFreq_5:
\ 000000F8 7080BDE8 POP {R4-R6,PC} ;; return
\ ??BSP_CPU_PclkFreq_3:
\ 000000FC A8C11FE0 DC32 0xffffffffe01fc1a8
\ 00000100 ACC11FE0 DC32 0xffffffffe01fc1ac
355 }
356 }
357
358 /*
359 *********************************************************************************************************
360 * DISABLE ALL INTERRUPTS
361 *
362 * Description : This function disables all interrupts from the interrupt controller.
363 *
364 * Arguments : none
365 *
366 * Returns : None
367 *********************************************************************************************************
368 */
369
\ In segment CODE, align 4, keep-with-next
370 void BSP_IntDisAll (void)
371 {
372 VICIntEnClear = 0xFFFFFFFFL; /* Disable ALL interrupts */
\ BSP_IntDisAll:
\ 00000000 EB00E0E3 MVN R0,#+235
\ 00000004 F00EC0E3 BIC R0,R0,#0xF00
\ 00000008 0010E0E3 MVN R1,#+0
\ 0000000C 001080E5 STR R1,[R0, #+0]
373 }
\ 00000010 0EF0A0E1 MOV PC,LR ;; return
374
375 /*
376 *********************************************************************************************************
377 * EXCEPTION HANDLER
378 *
379 * Description : This function should be used to handle any exceptions. It is called by
380 * OS_CPU_ARM_EXCEPT_HANDLER(), which is declared in os_cpu_a.s
381 *
382 * Arguments : ID, an identifier used to indicate what type of ARM exception has been triggered
383 * Possible ID values are shown below.
384 * OS_CPU_ARM_EXCEPT_RESET 0x00
385 * OS_CPU_ARM_EXCEPT_UNDEF_INSTR 0x01
386 * OS_CPU_ARM_EXCEPT_SWI 0x02
387 * OS_CPU_ARM_EXCEPT_PREFETCH_ABORT 0x03
388 * OS_CPU_ARM_EXCEPT_DATA_ABORT 0x04
389 * OS_CPU_ARM_EXCEPT_ADDR_ABORT 0x05
390 * OS_CPU_ARM_EXCEPT_IRQ 0x06
391 * OS_CPU_ARM_EXCEPT_FIQ 0x07
392 *********************************************************************************************************
393 */
394
\ In segment CODE, align 4, keep-with-next
395 void OS_CPU_ExceptHndlr (CPU_DATA ID)
396 {
\ OS_CPU_ExceptHndlr:
\ 00000000 30402DE9 PUSH {R4,R5,LR}
\ 00000004 0040B0E1 MOVS R4,R0
397 BSP_FNCT_PTR pfnct;
398
399 /* If this exception is either an IRQ or FIQ */
400 if ((ID == OS_CPU_ARM_EXCEPT_IRQ) || (ID == OS_CPU_ARM_EXCEPT_FIQ)) {
\ 00000008 060054E3 CMP R4,#+6
\ 0000000C 0100000A BEQ ??OS_CPU_ExceptHndlr_0
\ 00000010 070054E3 CMP R4,#+7
\ 00000014 0A00001A BNE ??OS_CPU_ExceptHndlr_1
401 pfnct = (BSP_FNCT_PTR)VICAddress; /* Read the interrupt vector from the VIC */
\ ??OS_CPU_ExceptHndlr_0:
\ 00000018 FF00E0E3 MVN R0,#+255
\ 0000001C 000090E5 LDR R0,[R0, #+0]
\ 00000020 0050B0E1 MOVS R5,R0
402 if (pfnct != (BSP_FNCT_PTR)0) { /* Make sure we don't have a NULL pointer */
\ 00000024 000055E3 CMP R5,#+0
\ 00000028 0500000A BEQ ??OS_CPU_ExceptHndlr_1
403 (*pfnct)(); /* Execute the ISR for the interrupting device */
\ 0000002C 0500B0E1 MOVS R0,R5
\ 00000030 0FE0A0E1 MOV LR,PC
\ 00000034 00F0A0E1 MOV PC,R0
404 VICAddress = 1; /* Acknowlege the VIC interrupt */
\ 00000038 FF00E0E3 MVN R0,#+255
\ 0000003C 0110A0E3 MOV R1,#+1
\ 00000040 001080E5 STR R1,[R0, #+0]
405 }
406 }
407 }
\ ??OS_CPU_ExceptHndlr_1:
\ 00000044 3080BDE8 POP {R4,R5,PC} ;; return
408
409 /*
410 ******************************************************************************************************************************
411 ******************************************************************************************************************************
412 ** OS-View Functions
413 ******************************************************************************************************************************
414 ******************************************************************************************************************************
415 */
416
417 /*
418 *********************************************************************************************************
419 * INITIALIZE TIMER FOR uC/OS-View
420 *
421 * Description : This function is called to by uC/OS-View to initialize the free running timer that is
422 * used to make time measurements.
423 *
424 * Arguments : none
425 *
426 * Returns ; none
427 *********************************************************************************************************
428 */
429
430 #if OS_VIEW_MODULE > 0
\ In segment CODE, align 4, keep-with-next
431 void OSView_TmrInit (void)
432 {
433 T1PR = 0;
\ OSView_TmrInit:
\ 00000000 CE02A0E3 MOV R0,#-536870900
\ 00000004 800C80E3 ORR R0,R0,#0x8000
\ 00000008 0010A0E3 MOV R1,#+0
\ 0000000C 001080E5 STR R1,[R0, #+0]
434 T1TCR = 0x00000001; /* Enable the timer */
\ 00000010 4E02A0E3 MOV R0,#-536870908
\ 00000014 800C80E3 ORR R0,R0,#0x8000
\ 00000018 0110A0E3 MOV R1,#+1
\ 0000001C 001080E5 STR R1,[R0, #+0]
435
436 }
\ 00000020 0EF0A0E1 MOV PC,LR ;; return
437 #endif
438
439 /*
440 *********************************************************************************************************
441 * READ TIMER FOR uC/OS-View
442 *
443 * Description : This function is called to read the current counts of a 32 bit free running timer.
444 *
445 * Arguments : none
446 *
447 * Returns ; The 32 bit counts of the timer assuming the timer (MUST be an UP counter).
448 *********************************************************************************************************
449 */
450
451 #if OS_VIEW_MODULE > 0
\ In segment CODE, align 4, keep-with-next
452 CPU_INT32U OSView_TmrRd (void)
453 {
454 if (OSRunning == DEF_TRUE) {
\ OSView_TmrRd:
\ 00000000 20009FE5 LDR R0,??OSView_TmrRd_0 ;; OSRunning
\ 00000004 0000D0E5 LDRB R0,[R0, #+0]
\ 00000008 010050E3 CMP R0,#+1
\ 0000000C 0300001A BNE ??OSView_TmrRd_1
455 return ((CPU_INT32U)T1TC);
\ 00000010 8E02A0E3 MOV R0,#-536870904
\ 00000014 800C80E3 ORR R0,R0,#0x8000
\ 00000018 000090E5 LDR R0,[R0, #+0]
\ 0000001C 000000EA B ??OSView_TmrRd_2
456 } else {
457 return (0);
\ ??OSView_TmrRd_1:
\ 00000020 0000A0E3 MOV R0,#+0
\ ??OSView_TmrRd_2:
\ 00000024 0EF0A0E1 MOV PC,LR ;; return
\ ??OSView_TmrRd_0:
\ 00000028 ........ DC32 OSRunning
458 }
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