📄 bsp.lst
字号:
223
224 /*
225 *********************************************************************************************************
226 * Get the CPU Clock Frequency
227 *
228 * Description : This function reads CPU registers to determine the CPU clock frequency
229 *
230 * Arguements : None
231 *
232 * Returns : The CPU Core clock in Hz
233 *
234 * Notes : None
235 *********************************************************************************************************
236 */
237
\ In segment CODE, align 4, keep-with-next
238 CPU_INT32U BSP_CPU_ClkFreq (void)
239 {
\ BSP_CPU_ClkFreq:
\ 00000000 F0402DE9 PUSH {R4-R7,LR}
240 CPU_INT32U msel;
241 CPU_INT32U nsel;
242 CPU_INT32U fin;
243 CPU_INT32U pll_clk_feq; /* When the PLL is enabled, this is Fcco */
244 CPU_INT32U clk_div;
245 CPU_INT32U clk_freq;
246
247
248 switch (CLKSRCSEL & 0x03) { /* Determine the current clock source */
\ 00000004 E0009FE5 LDR R0,??BSP_CPU_ClkFreq_1 ;; 0xffffffffe01fc10c
\ 00000008 000090E5 LDR R0,[R0, #+0]
\ 0000000C 030010E2 ANDS R0,R0,#0x3
\ 00000010 020050E3 CMP R0,#+2
\ 00000014 0E00008A BHI ??BSP_CPU_ClkFreq_2
\ 00000018 011F8FE2 ADR R1,??BSP_CPU_ClkFreq_0
\ 0000001C 0010D1E7 LDRB R1,[R1, R0]
\ 00000020 01F18FE0 ADD PC,PC,R1, LSL #+2
\ ??BSP_CPU_ClkFreq_0:
\ 00000024 00040800 DC8 +0,+4,+8,+0
249 case 0:
250 fin = IRC_OSC_FRQ;
\ ??BSP_CPU_ClkFreq_3:
\ 00000028 B708A0E3 MOV R0,#+11993088
\ 0000002C 6C0D80E3 ORR R0,R0,#0x1B00
\ 00000030 0040B0E1 MOVS R4,R0
\ 00000034 090000EA B ??BSP_CPU_ClkFreq_4
251 break;
252
253 case 1:
254 fin = MAIN_OSC_FRQ;
\ ??BSP_CPU_ClkFreq_5:
\ 00000038 B708A0E3 MOV R0,#+11993088
\ 0000003C 6C0D80E3 ORR R0,R0,#0x1B00
\ 00000040 0040B0E1 MOVS R4,R0
\ 00000044 050000EA B ??BSP_CPU_ClkFreq_4
255 break;
256
257 case 2:
258 fin = RTC_OSC_FRQ;
\ ??BSP_CPU_ClkFreq_6:
\ 00000048 800CA0E3 MOV R0,#+32768
\ 0000004C 0040B0E1 MOVS R4,R0
\ 00000050 020000EA B ??BSP_CPU_ClkFreq_4
259 break;
260
261 default:
262 fin = IRC_OSC_FRQ;
\ ??BSP_CPU_ClkFreq_2:
\ 00000054 B708A0E3 MOV R0,#+11993088
\ 00000058 6C0D80E3 ORR R0,R0,#0x1B00
\ 0000005C 0040B0E1 MOVS R4,R0
263 break;
264 }
265
266 if ((PLLSTAT & (1 << 25)) > 0) { /* If the PLL is currently enabled and connected */
\ ??BSP_CPU_ClkFreq_4:
\ 00000060 88009FE5 LDR R0,??BSP_CPU_ClkFreq_1+0x4 ;; 0xffffffffe01fc088
\ 00000064 000090E5 LDR R0,[R0, #+0]
\ 00000068 800710E3 TST R0,#0x2000000
\ 0000006C 1200000A BEQ ??BSP_CPU_ClkFreq_7
267 msel = (CPU_INT32U)(PLLSTAT & 0x3FFF) + 1; /* Obtain the PLL multiplier */
\ 00000070 78009FE5 LDR R0,??BSP_CPU_ClkFreq_1+0x4 ;; 0xffffffffe01fc088
\ 00000074 000090E5 LDR R0,[R0, #+0]
\ 00000078 0009B0E1 LSLS R0,R0,#+18
\ 0000007C 0110A0E3 MOV R1,#+1
\ 00000080 200991E0 ADDS R0,R1,R0, LSR #+18
\ 00000084 0020B0E1 MOVS R2,R0
268 nsel = (CPU_INT32U)((PLLSTAT >> 16) & 0x0F) + 1; /* Obtain the PLL divider */
\ 00000088 60009FE5 LDR R0,??BSP_CPU_ClkFreq_1+0x4 ;; 0xffffffffe01fc088
\ 0000008C 000090E5 LDR R0,[R0, #+0]
\ 00000090 0F10A0E3 MOV R1,#+15
\ 00000094 200811E0 ANDS R0,R1,R0, LSR #+16
\ 00000098 010090E2 ADDS R0,R0,#+1
\ 0000009C 0030B0E1 MOVS R3,R0
269 pll_clk_feq = (2 * msel * fin / nsel); /* Compute the PLL output frequency */
\ 000000A0 940210E0 MULS R0,R4,R2
\ 000000A4 0210A0E3 MOV R1,#+2
\ 000000A8 910010E0 MULS R0,R1,R0
\ 000000AC 0310B0E1 MOVS R1,R3
\ 000000B0 ........ _BLF ??divu32_a,??rA??divu32_a
\ 000000B4 0150B0E1 MOVS R5,R1
\ 000000B8 000000EA B ??BSP_CPU_ClkFreq_8
270 } else {
271 pll_clk_feq = (fin); /* The PLL is bypassed */
\ ??BSP_CPU_ClkFreq_7:
\ 000000BC 0450B0E1 MOVS R5,R4
272 }
273
274 clk_div = (CPU_INT08U)(CCLKCFG & 0x0F) + 1; /* Obtain the CPU core clock divider */
\ ??BSP_CPU_ClkFreq_8:
\ 000000C0 2C009FE5 LDR R0,??BSP_CPU_ClkFreq_1+0x8 ;; 0xffffffffe01fc104
\ 000000C4 000090E5 LDR R0,[R0, #+0]
\ 000000C8 0F0010E2 ANDS R0,R0,#0xF
\ 000000CC 010090E2 ADDS R0,R0,#+1
\ 000000D0 0060B0E1 MOVS R6,R0
275 clk_freq = (CPU_INT32U)(pll_clk_feq / clk_div); /* Compute the ARM Core clock frequency */
\ 000000D4 0500B0E1 MOVS R0,R5
\ 000000D8 0610B0E1 MOVS R1,R6
\ 000000DC ........ _BLF ??divu32_a,??rA??divu32_a
\ 000000E0 0170B0E1 MOVS R7,R1
276
277 return (clk_freq);
\ 000000E4 0700B0E1 MOVS R0,R7
\ 000000E8 F080BDE8 POP {R4-R7,PC} ;; return
\ ??BSP_CPU_ClkFreq_1:
\ 000000EC 0CC11FE0 DC32 0xffffffffe01fc10c
\ 000000F0 88C01FE0 DC32 0xffffffffe01fc088
\ 000000F4 04C11FE0 DC32 0xffffffffe01fc104
278 }
279
280 /*
281 *********************************************************************************************************
282 * Get a Peripheral Clock Frequency
283 *
284 * Description : This function reads CPU registers to determine the the clock frequency for the specified
285 * peripheral
286 *
287 * Arguements : An ID, one of PCLK_??? defined in bsp.c
288 *
289 * Returns : The peripheral's clock in Hz
290 *********************************************************************************************************
291 */
292
293
\ In segment CODE, align 4, keep-with-next
294 CPU_INT32U BSP_CPU_PclkFreq (CPU_INT08U pclk)
295 {
\ BSP_CPU_PclkFreq:
\ 00000000 70402DE9 PUSH {R4-R6,LR}
\ 00000004 0040B0E1 MOVS R4,R0
296 CPU_INT32U clk_freq;
297 CPU_INT32U selection;
298
299
300 clk_freq = BSP_CPU_ClkFreq();
\ 00000008 ........ BL BSP_CPU_ClkFreq
\ 0000000C 0050B0E1 MOVS R5,R0
301
302 switch (pclk) {
\ 00000010 0400B0E1 MOVS R0,R4
\ 00000014 1D0050E3 CMP R0,#+29
\ 00000018 3500008A BHI ??BSP_CPU_PclkFreq_1
\ 0000001C 011F8FE2 ADR R1,??BSP_CPU_PclkFreq_0
\ 00000020 0010D1E7 LDRB R1,[R1, R0]
\ 00000024 01F18FE0 ADD PC,PC,R1, LSL #+2
\ ??BSP_CPU_PclkFreq_0:
\ 00000028 07070707 DC8 +7,+7,+7,+7
\ 0000002C 07070707 DC8 +7,+7,+7,+7
\ 00000030 07070707 DC8 +7,+7,+7,+7
\ 00000034 07070707 DC8 +7,+7,+7,+7
\ 00000038 1C1C1C1C DC8 +28,+28,+28,+28
\ 0000003C 321C1C1C DC8 +50,+28,+28,+28
\ 00000040 1C1C1C1C DC8 +28,+28,+28,+28
\ 00000044 321C0000 DC8 +50,+28,+0,+0
303 case PCLK_WDT:
304 case PCLK_TIMER0:
305 case PCLK_TIMER1:
306 case PCLK_UART0:
307 case PCLK_UART1:
308 case PCLK_PWM0:
309 case PCLK_PWM1:
310 case PCLK_I2C0:
311 case PCLK_SPI:
312 case PCLK_RTC:
313 case PCLK_SSP1:
314 case PCLK_DAC:
315 case PCLK_ADC:
316 case PCLK_CAN1:
317 case PCLK_CAN2:
318 case PCLK_ACF:
319 selection = ((PCLKSEL0 >> (pclk * 2)) & 0x03);
\ ??BSP_CPU_PclkFreq_2:
\ 00000048 AC009FE5 LDR R0,??BSP_CPU_PclkFreq_3 ;; 0xffffffffe01fc1a8
\ 0000004C 000090E5 LDR R0,[R0, #+0]
\ 00000050 0210A0E3 MOV R1,#+2
\ 00000054 910412E0 MULS R2,R1,R4
\ 00000058 0310A0E3 MOV R1,#+3
\ 0000005C 300211E0 ANDS R0,R1,R0, LSR R2
\ 00000060 0060B0E1 MOVS R6,R0
320 if (selection == 0) {
\ 00000064 000056E3 CMP R6,#+0
\ 00000068 0100001A BNE ??BSP_CPU_PclkFreq_4
321 return (clk_freq / 4);
\ 0000006C 2501B0E1 LSRS R0,R5,#+2
\ 00000070 200000EA B ??BSP_CPU_PclkFreq_5
322 } else if (selection == 1) {
\ ??BSP_CPU_PclkFreq_4:
\ 00000074 010056E3 CMP R6,#+1
\ 00000078 0100001A BNE ??BSP_CPU_PclkFreq_6
323 return (clk_freq);
\ 0000007C 0500B0E1 MOVS R0,R5
\ 00000080 1C0000EA B ??BSP_CPU_PclkFreq_5
324 } else if (selection == 2) {
\ ??BSP_CPU_PclkFreq_6:
\ 00000084 020056E3 CMP R6,#+2
\ 00000088 0100001A BNE ??BSP_CPU_PclkFreq_7
325 return (clk_freq / 2);
\ 0000008C A500B0E1 LSRS R0,R5,#+1
\ 00000090 180000EA B ??BSP_CPU_PclkFreq_5
326 } else {
327 return (clk_freq / 8);
\ ??BSP_CPU_PclkFreq_7:
\ 00000094 A501B0E1 LSRS R0,R5,#+3
\ 00000098 160000EA B ??BSP_CPU_PclkFreq_5
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -