📄 pxa-regs.h
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#define GPIO70_LDD_12 70 /* LCD data pin 12 */#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */#define GPIO71_LDD_13 71 /* LCD data pin 13 */#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */#define GPIO72_LDD_14 72 /* LCD data pin 14 */#define GPIO72_32kHz 72 /* 32 kHz clock */#define GPIO73_LDD_15 73 /* LCD data pin 15 */#define GPIO73_MBGNT 73 /* Memory controller grant */#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */#define GPIO75_LCD_LCLK 75 /* LCD line clock */#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */#define GPIO78_nCS_2 78 /* chip select 2 */#define GPIO79_nCS_3 79 /* chip select 3 */#define GPIO80_nCS_4 80 /* chip select 4 */#define GPIO81_NSCLK 81 /* NSSP clock */#define GPIO82_NSFRM 82 /* NSSP Frame */#define GPIO83_NSTXD 83 /* NSSP transmit */#define GPIO84_NSRXD 84 /* NSSP receive */#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */#define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */#define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) *//* GPIO alternate function mode & direction */#define GPIO_IN 0x000#define GPIO_OUT 0x080#define GPIO_ALT_FN_1_IN 0x100#define GPIO_ALT_FN_1_OUT 0x180#define GPIO_ALT_FN_2_IN 0x200#define GPIO_ALT_FN_2_OUT 0x280#define GPIO_ALT_FN_3_IN 0x300#define GPIO_ALT_FN_3_OUT 0x380#define GPIO_ACTIVE_LOW 0x1000#define GPIO_MD_MASK_NR 0x07f#define GPIO_MD_MASK_DIR 0x080#define GPIO_MD_MASK_FN 0x300#define GPIO_DFLT_LOW 0x400#define GPIO_DFLT_HIGH 0x800#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)#define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT)#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT | GPIO_ACTIVE_LOW)#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT)#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)#define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT)#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)#define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT)#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)#define GPIO32_MMCCLK_MD ( 32 | GPIO_ALT_FN_2_OUT)#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT | GPIO_ACTIVE_LOW)#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT | GPIO_ACTIVE_LOW)#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT | GPIO_ACTIVE_LOW)#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT | GPIO_ACTIVE_LOW)#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT | GPIO_ACTIVE_LOW)#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT | GPIO_ACTIVE_LOW)#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT | GPIO_ACTIVE_LOW)#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)#define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT)#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT | GPIO_ACTIVE_LOW)#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT | GPIO_ACTIVE_LOW)#define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT)#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT | GPIO_ACTIVE_LOW)#define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT)#define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN)#define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT)#define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN)#define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT)#define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN)#define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT)#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT)#define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT)#define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT)#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_OUT)#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)/* * Power Manager */#define PMCR __REG(0x40F00000) /* Power Manager Control Register */#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */#define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */#define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */#define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */#define PCMD(x) __REG2(0x40F00080, (x)<<2)#define PCMD0 __REG(0x40F00080 + 0 * 4)#define PCMD1 __REG(0x40F00080 + 1 * 4)#define PCMD2 __REG(0x40F00080 + 2 * 4)#define PCMD3 __REG(0x40F00080 + 3 * 4)#define PCMD4 __REG(0x40F00080 + 4 * 4)#define PCMD5 __REG(0x40F00080 + 5 * 4)#define PCMD6 __REG(0x40F00080 + 6 * 4)#define PCMD7 __REG(0x40F00080 + 7 * 4)#define PCMD8 __REG(0x40F00080 + 8 * 4)#define PCMD9 __REG(0x40F00080 + 9 * 4)#define PCMD10 __REG(0x40F00080 + 10 * 4)#define PCMD11 __REG(0x40F00080 + 11 * 4)#define PCMD12 __REG(0x40F00080 + 12 * 4)#define PCMD13 __REG(0x40F00080 + 13 * 4)#define PCMD14 __REG(0x40F00080 + 14 * 4)#define PCMD15 __REG(0x40F00080 + 15 * 4)#define PCMD16 __REG(0x40F00080 + 16 * 4)#define PCMD17 __REG(0x40F00080 + 17 * 4)#define PCMD18 __REG(0x40F00080 + 18 * 4)#define PCMD19 __REG(0x40F00080 + 19 * 4)#define PCMD20 __REG(0x40F00080 + 20 * 4)#define PCMD21 __REG(0x40F00080 + 21 * 4)#define PCMD22 __REG(0x40F00080 + 22 * 4)#define PCMD23 __REG(0x40F00080 + 23 * 4)#define PCMD24 __REG(0x40F00080 + 24 * 4)#define PCMD25 __REG(0x40F00080 + 25 * 4)#define PCMD26 __REG(0x40F00080 + 26 * 4)#define PCMD27 __REG(0x40F00080 + 27 * 4)#define PCMD28 __REG(0x40F00080 + 28 * 4)#define PCMD29 __REG(0x40F00080 + 29 * 4)#define PCMD30 __REG(0x40F00080 + 30 * 4)#define PCMD31 __REG(0x40F00080 + 31 * 4)#define PCMD_MBC (1<<12)#define PCMD_DCE (1<<11)#define PCMD_LC (1<<10)/* FIXME: PCMD_SQC need be checked. */#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, bit 9 should be 0 all day. */#define PVCR_VCSA (0x1<<14)#define PVCR_CommandDelay (0xf80)#define PCFR_PI2C_EN (0x1 << 6)#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */#define PSSR_RDH (1 << 5) /* Read Disable Hold */#define PSSR_PH (1 << 4) /* Peripheral Control Hold */#define PSSR_VFS (1 << 2) /* VDD Fault Status */#define PSSR_BFS (1 << 1) /* Battery Fault Status */#define PSSR_SSS (1 << 0) /* Software Sleep Status */#define PCFR_RO (1 << 15) /* RDH Override */#define PCFR_PO (1 << 14) /* PH Override */#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */#define PCFR_FVC (1 << 10) /* Freque⌨️ 快捷键说明
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