dalingkongzhiqi.txt

24小时打铃控制器

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity timer is
PORT(
	scanclk,adj_h_in,adj_m_in,set,close,adj_noon_in,reset_in: in std_logic;
	led_out: out std_logic_vector(6 downto 0);
	scan_out:   out integer range 0 to 5;
	sound_out:   out std_logic;
            s_out:   out std_logic;
         noon_out: out std_logic;     
	point_out:   out std_logic );
end timer;
architecture rtl of timer IS
	signal scan: integer range 0 to 5;
	signal clk1s: std_logic;
	signal sound,sound1,sound2,sound3: std_logic;
	signal reset,adj_h,adj_m: std_logic;
	signal c_h_en, c_mh_en, c_ml_en, c_sh_en : std_logic;
	signal c_h_en1, c_ml_en1 : std_logic;
	signal c_mh_en1 : std_logic;
	signal enable,disable: std_logic;
	signal c_mh,mh,sh: integer range 0 to 5;
	signal cnt: std_logic_vector( 10 downto 0);
        signal adj_noon:std_logic;
        signal s:std_logic_vector(1 downto 0);
        signal sound_control:std_logic;
	signal hh,hl,ml,sl: integer range 0 to 9;
	signal c_ml: integer range 0 to 9;
	signal c_h,h: integer range 0 to 23;
	signal hex: integer range 0 to 10;
        signal s_l: integer range 0 to 19;
        signal noon:std_logic;
	signal led:std_logic_vector (6 downto 0);
	
	component counter IS
		GENERIC( count_value: INTEGER);
		PORT
		(	clk,clr,en			: IN	STD_LOGIC;
			co				: OUT	STD_LOGIC;
			count				: OUT 	INTEGER RANGE 0 TO count_value);
	END component;

BEGIN
----------------- counter part -------------------
	generat_1s_clock: PROCESS (scanclk)
	BEGIN
		IF (scanclk'EVENT AND scanclk = '1') THEN
			cnt <= cnt + 1;
		END IF;
                        clk1s <= cnt(9);
        END PROCESS;
	
	enable<='1';
	disable<='0';

	reset<=not reset_in;
	adj_m<=not adj_m_in;
	adj_h<=not adj_h_in;
        adj_noon<=not adj_noon_in;
	
	CNT1S: counter
	generic map( count_value => 9)
	port map(clk=>CLK1s,clr=>reset,en=>enable,co=>c_sh_en,count=>sl);
	CNT10S: counter
	generic map( count_value => 5)
	port map(clk=>clk1s,clr=>reset,en=>c_sh_en,co=>c_ml_en1,count=>sh);
	CNT1M: counter
	generic map( count_value => 9)
	port map(clk=>clk1s,clr=>disable,en=>c_ml_en,co=>c_mh_en1,count=>c_ml);
	CNT10M: counter
	generic map( count_value => 5)
	port map(clk=>clk1s,clr=>disable,en=>c_mh_en,co=>c_h_en1,count=>c_mh);
	CNT_H: counter
	generic map( count_value => 24)
	port map(clk=>clk1s,clr=>disable,en=>c_h_en,count=>c_h);
        CNT20S: counter
	generic map( count_value => 19)
	port map(clk=>CLK1s,clr=>reset,en=>enable,count=>s_l);
	
	c_ml_en <= (not set and adj_m) or (c_ml_en1 and c_sh_en);
c_mh_en <= (c_mh_en1 and c_ml_en);
c_h_en  <= (not set and adj_h) or (c_h_en1 and c_mh_en);

----------------- compare part -------------------
process(s_l)
begin
     if(s_l<5)or(s_l>=7 and s_l<=12)then
             sound_control<= '1';
     else
             sound_control<= '0';
     end if;

end process;
sound1 <= scanclk when c_ml=0 and c_mh=0 and c_h=6 and  sound_control= '1' else '0';
sound2 <= scanclk when c_ml=0 and c_mh=3 and c_h=10 and  sound_control= '1' else '0';
sound<=sound1 or sound2;
sound_out <= sound when close = '0'  else '0';

process(set,adj_noon,c_h)
begin
     if set='0'and adj_noon='0'then
            noon<='0';
     elsif set='0'and adj_noon='1'then
            noon<='1';
     elsif  c_h>11  then
            noon<='1';
     elsif  c_h<=11  then
            noon<='0';
        
     end if;
end process;
noon_out<=noon;

----------------- select  part -------------------
hh<=1 when( h>=10 and h<12)or(h>=22 and h<24) else 
    0;
hl<=(h-0) when h<10 else
    (h-10)when h>=10 and h<12 else
    (h-12)when h>=12 and h<22 else
    (h-22);
h<=c_h ;
mh<=c_mh ;
ml<=c_ml;
s_out<=clk1s;

----------------- display part -------------------
process (scanclk)			       
begin
	if scanclk'event and scanclk='1' then
		if scan = 3 then
			scan<=0;
		else
			scan <= scan + 1;
		end if;
	end if;
end process;

with scan select
	hex<=hh when 3,
		 hl when 2,
		 mh when 1,
		 ml when 0;
		  
with scan select
	point_out <= clk1s when 2,
		     '0' when others;
	
led_out<= NOT led;
scan_out<=scan;
with hex select
	led<=   "1111001" when 1,    --1
	        "0100100" when 2,    --2
	        "0110000" when 3,    --3
	        "0011001" when 4,    --4
	        "0010010" when 5,    --5
	        "0000010" when 6,    --6
	        "1111000" when 7,    --7
	        "0000000" when 8,    --8
	        "0010000" when 9,    --9
	        "1000000" when 0,    --0
	        "1111111" when others; 
end rtl;