__projnav.log

fifo code. i have adde the code for key lib to the data which has been transfered

Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/users/keyb/keyb.vhd in Library work.
Entity <keyb> (Architecture <keyb_arch>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <keyb> (Architecture <keyb_arch>).
WARNING:Xst:766 - E:/users/keyb/keyb.vhd line 111: Generating a Black Box for component <PULLDOWN>.
WARNING:Xst:766 - E:/users/keyb/keyb.vhd line 112: Generating a Black Box for component <PULLDOWN>.
WARNING:Xst:766 - E:/users/keyb/keyb.vhd line 113: Generating a Black Box for component <PULLDOWN>.
WARNING:Xst:766 - E:/users/keyb/keyb.vhd line 289: Generating a Black Box for component <PULLUP>.
WARNING:Xst:766 - E:/users/keyb/keyb.vhd line 290: Generating a Black Box for component <PULLUP>.
WARNING:Xst:766 - E:/users/keyb/keyb.vhd line 291: Generating a Black Box for component <PULLUP>.
WARNING:Xst:819 - E:/users/keyb/keyb.vhd line 293: The following signals are missing in the process sensitivity list:
   clk_50k.
WARNING:Xst:819 - E:/users/keyb/keyb.vhd line 352: The following signals are missing in the process sensitivity list:
   pass_m.
Entity <keyb> analyzed. Unit <keyb> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <keyb>.
    Related source file is E:/users/keyb/keyb.vhd.
    Found finite state machine <FSM_0> for signal <k2b_state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 7                                              |
    | Inputs             | 2                                              |
    | Outputs            | 3                                              |
    | Clock              | clk_100 (rising_edge)                          |
    | Reset              | enable (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | k2b_idle                                       |
    | Power Up State     | k2b_idle                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <mp_state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 14                                             |
    | Inputs             | 5                                              |
    | Outputs            | 7                                              |
    | Clock              | clk_100 (rising_edge)                          |
    | Reset              | enable (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | mp_waituser                                    |
    | Power Up State     | mp_waituser                                    |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_2> for signal <fr_state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 10                                             |
    | Inputs             | 3                                              |
    | Outputs            | 7                                              |
    | Clock              | clk_50k (rising_edge)                          |
    | Reset              | enable (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | fr_idle                                        |
    | Power Up State     | fr_idle                                        |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_3> for signal <fw_state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 11                                             |
    | Inputs             | 3                                              |
    | Outputs            | 8                                              |
    | Clock              | clk_50k (rising_edge)                          |
    | Reset              | enable (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | fw_idle                                        |
    | Power Up State     | fw_idle                                        |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32x1-bit ROM for signal <key_err>.
    Found 4-bit tristate buffer for signal <row>.
    Found 18-bit tristate buffer for signal <flash_a>.
    Found 8-bit tristate buffer for signal <flash_d>.
    Found 1-bit tristate buffer for signal <flash_cen>.
    Found 1-bit tristate buffer for signal <flash_oen>.
    Found 1-bit tristate buffer for signal <enable>.
    Found 24-bit comparator equal for signal <$n0105> created at line 379.
    Found 8-bit comparator equal for signal <$n0116> created at line 484.
    Found 17-bit adder for signal <$n0148> created at line 503.
    Found 16-bit adder for signal <$n0149> created at line 576.
    Found 18-bit adder for signal <$n0150>.
    Found 2-bit comparator equal for signal <$n0198> created at line 134.
    Found 18-bit subtractor for signal <$n0202> created at line 492.
    Found 2-bit adder for signal <$n0203> created at line 614.
    Found 18-bit adder for signal <$n0207> created at line 603.
    Found 1-bit register for signal <clk_100>.
    Found 8-bit up counter for signal <clk_ctr>.
    Found 3-bit register for signal <col_save>.
    Found 3-bit up counter for signal <count>.
    Found 10-bit down counter for signal <err_ctr>.
    Found 18-bit register for signal <flash_abufr>.
    Found 18-bit register for signal <flash_abufw>.
    Found 2-bit register for signal <fw_bytectr>.
    Found 7-bit down counter for signal <led_ctr>.
    Found 24-bit register for signal <pass>.
    Found 24-bit register for signal <pass_m>.
    Found 10-bit down counter for signal <res_ctr>.
    Found 2-bit up counter for signal <row_count>.
    Found 2-bit register for signal <row_save>.
    Found 8-bit register for signal <user>.
    Found 24-bit register for signal <value>.
    Found 9 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   4 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred   6 Counter(s).
	inferred 124 D-type flip-flop(s).
	inferred   6 Adder/Subtracter(s).
	inferred   3 Comparator(s).
	inferred   9 Multiplexer(s).
	inferred  56 Tristate(s).
Unit <keyb> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 4
# ROMs                             : 1
  32x1-bit ROM                     : 1
# Registers                        : 10
  18-bit register                  : 2
  2-bit register                   : 2
  1-bit register                   : 1
  3-bit register                   : 1
  24-bit register                  : 3
  8-bit register                   : 1
# Counters                         : 6
  8-bit up counter                 : 1
  2-bit up counter                 : 1
  3-bit up counter                 : 1
  10-bit down counter              : 2
  7-bit down counter               : 1
# Multiplexers                     : 9
  2-to-1 multiplexer               : 9
# Tristates                        : 22
  1-bit tristate buffer            : 20
  18-bit tristate buffer           : 2
# Adders/Subtractors               : 6
  17-bit adder                     : 1
  16-bit adder                     : 1
  18-bit adder                     : 2
  18-bit subtractor                : 1
  2-bit adder                      : 1
# Comparators                      : 3
  24-bit comparator equal          : 1
  8-bit comparator equal           : 1
  2-bit comparator equal           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
Selecting encoding for FSM_3 ...
Optimizing FSM <FSM_3> on signal <fw_state> with one-hot encoding.
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <fr_state> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <mp_state> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <k2b_state> with one-hot encoding.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <flash_abufw_0> (without init value) is constant in block <keyb>.
WARNING:Xst:1710 - FF/Latch  <flash_abufw_1> (without init value) is constant in block <keyb>.

Optimizing unit <keyb> ...
Loading device for application Xst from file 'v50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block keyb, actual ratio is 37.
FlipFlop clk_100 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                     251  out of    768    32%  
 Number of Slice Flip Flops:           186  out of   1536    12%  
 Number of 4 input LUTs:               443  out of   1536    28%  
 Number of bonded IOBs:                 38  out of     96    39%  
 Number of TBUFs:                       44  out of    768     5%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_50k                            | BUFGP                  | 83    |
clk_100_1:Q                        | NONE                   | 52    |
clk_100:Q                          | NONE                   | 51    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 29.006ns (Maximum Frequency: 34.476MHz)
   Minimum input arrival time before clock: 6.693ns
   Maximum output required time after clock: 20.974ns
   Maximum combinational path delay: 14.542ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\users\keyb/_ngo -uc keyb.ucf -p
xc2s50-tq144-5 keyb.ngc keyb.ngd 

Reading NGO file "E:/users/keyb/keyb.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "keyb.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'clk_50k_BUFGP' has non-clock connections.
   These problematic connections include:
     pin I2 on block flash_wen21 with type LUT3
WARNING:NgdBuild:483 - Attribute "INIT" on "mp_state_FFd1" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "mp_state_FFd6" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "k2b_state_FFd2" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "k2b_state_FFd1" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "mp_state_FFd2" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "mp_state_FFd3" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "mp_state_FFd5" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "mp_state_FFd7" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "mp_state_FFd4" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "fr_state_FFd4" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "fr_state_FFd2" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "fr_state_FFd1" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "fr_state_FFd3" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "fr_state_FFd6" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "fr_state_FFd5" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "fw_state_FFd3" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "fw_state_FFd2" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "fw_state_FFd7" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on "fw_state_FFd1" is on the wrong type
   of object.  Please see the Constraints Guide for more information on this
   attribute.