vhdl.api

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abs
access
add
after
alias
all
and
architecture
array
assert
attribute
begin
block
body
buffer
bus
case
component
configuration
constant
downto
else
elsif
end
entity
error
exit
for
file
function
generate
generic
group
if
in
inout
inertial
impure
is
label
library
loop
map
mod
nand
next
nor
not
null
of
on
or
others
out
package
port
procedure
process
pure
range
record
reject
rem
report
register
return
rol
ror
select
severity
signal
sla
sll
sra
srl
subtype
then
transport
to
type
unaffected
until
use
variable
wait
when
while
with
xnor
xor